參數(shù)資料
型號(hào)： EDE5104AESK-6E-E
廠商： ELPIDA MEMORY INC
元件分類： DRAM
英文描述： 512M bits DDR2 SDRAM
中文描述： 128M X 4 DDR DRAM, 0.45 ns, PBGA60
封裝： ROHS COMPLIANT, FBGA-60
文件頁數(shù)： 38/66頁
文件大?。?/td> 697K
代理商： EDE5104AESK-6E-E
EDE5104ABSE, EDE5108ABSE, EDE5116ABSE
Data Sheet E0323E90 (Ver. 9.0)
38
Read and Write Access Modes
After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting /RAS high,
/CS and /CAS low at the clock’s rising edge. /WE must also be defined at this time to determine whether the access
cycle is a read operation (/WE high) or a write operation (/WE low).
The DDR2 SDRAM provides a fast column access operation. A single read or write command will initiate a serial
read or write operation on successive clock cycles. The boundary of the burst cycle is strictly restricted to specific
segments of the page length. For example, the 32M bits
×
4 I/O
×
4 banks chip has a page length of 2048 bits
(defined by CA0 to CA9, CA11). The page length of 2048 is divided into 512 uniquely addressable boundary
segments (4 bits each). A 4 bits burst operation will occur entirely within one of the 512 groups beginning with the
column address supplied to the device during the read or write command (CA0 to CA9, CA11). The second, third
and fourth access will also occur within this group segment, however, the burst order is a function of the starting
address, and the burst sequence.
A new burst access must not interrupt the previous 4-bit burst operation. The minimum /CAS to /CAS delay is
defined by tCCD, and is a minimum of 2 clocks for read or write cycles.
Posted /CAS
Posted /CAS operation is supported to make command and data bus efficient for sustainable bandwidths in DDR2
SDRAM. In this operation, the DDR2 SDRAM allows a /CAS read or write command to be issued immediately after
the /RAS bank activate command (or any time during the /RAS-/CAS-delay time, tRCD, period). The command is
held for the time of the Additive Latency (AL) before it is issued inside the device. The Read Latency (RL) is
controlled by the sum of AL and the /CAS latency (CL). Therefore if a user chooses to issue a R/W command before
the tRCD (min), then AL (greater than 0) must be written into the EMRS. The Write Latency (WL) is always defined
as RL
1 (read latency
1) where read latency is defined as the sum of additive latency plus /CAS latency (RL = AL
+ CL).
-1
/CK
CK
DQS, /DQS
AL = 2
>
tRCD
=
>
tRAC
=
CL = 3
Command
DQ
0
1
2
3
4
5
6
7
8
9
10
11
12
ACT
READ
NOP
NOP
WRIT
out0 out1 out2 out3
in0 in1 in2 in3
WL = RL n–1 = 4
RL = AL + CL = 5
Read Followed by a Write to the Same Bank
[AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL - 1) = 4]
-1
0
1
2
3
4
5
6
7
8
9
10
11
12
/CK
CK
DQS, /DQS
AL = 0
READ
>
tRCD
=
>
tRAC
=
CL = 3
Command
DQ
ACT
WRIT
out0 out1 out2 out3
in0 in1 in2 in3
RL = AL + CL = 3
WL = RL n–1 = 2
NOP
NOP
NOP
Read Followed by a Write to the Same Bank
[AL = 0 and CL = 3, RL = (AL + CL) = 3, WL = (RL - 1) = 2]
相關(guān)PDF資料
PDF描述
EDE5104GBSA-4A-E 512M bits DDR-II SDRAM
EDE5104AJSE EDE5104AJSE
EDE5108AJBG 512M bits DDR2 SDRAM
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EDE5104AGSE 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM
EDE5104AGSE_1 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM
EDE5104AGSE-4A-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM
EDE5104AGSE-5C-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM
EDE5104AGSE-6C-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM
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