參數資料
型號： EDD1232AAFA-6B-E
廠商： ELPIDA MEMORY INC
元件分類： DRAM
英文描述： 128M bits DDR SDRAM (4M words x 32 bits)
中文描述： 4M X 32 DDR DRAM, 0.7 ns, PQFP100
封裝： ROHS COMPLIANT, PLASTIC, LQFP-100
文件頁數： 5/50頁
文件大小： 621K
代理商： EDD1232AAFA-6B-E
EDD1232AABH
Data Sheet E0533E50 (Ver. 5.0)
5
Electrical Specifications
All voltages are referenced to VSS (GND).
After power up, wait more than 200 μs and then, execute power on sequence and CBR (Auto) refresh before
proper device operation is achieved.
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Note
Voltage on any pin relative to VSS
VT
–1.0 to +3.6
V
Supply voltage relative to VSS
VDD
–1.0 to +3.6
V
Short circuit output current
IOS
50
mA
Power dissipation
PD
1.0
W
Operating ambient temperature
TA
0 to +70
°
C
Storage temperature
Tstg
–55 to +125
°
C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (TA = 0 to +70
°
C)
Parameter
Symbol
min.
typ.
max.
Unit
Notes
Supply voltage
VDD,
VDDQ
VSS,
VSSQ
2.3
2.5
2.7
V
1
0
0
0
V
Input reference voltage
VREF
0.49
×
VDDQ
0.50
×
VDDQ 0.51
×
VDDQ
V
Termination voltage
VTT
VREF – 0.04
VREF
VREF + 0.04
V
Input high voltage
VIH (DC)
VREF + 0.15
—
VDDQ + 0.3
V
2
Input low voltage
VIL (DC)
–0.3
—
VREF – 0.15
V
3
Input voltage level,
CK and /CK inputs
Input differential cross point
voltage, CK and /CK inputs
Input differential voltage,
CK and /CK inputs
Notes: 1. VDDQ must be lower than or equal to VDD.
2. VIH is allowed to exceed VDD up to 3.6V for the period shorter than or equal to 5ns.
3. VIL is allowed to outreach below VSS down to –1.0V for the period shorter than or equal to 5ns.
4. VIN (DC) specifies the allowable DC execution of each differential input.
5. VID (DC) specifies the input differential voltage required for switching.
6. VIH (CK) min assumed over VREF + 0.18V, VIL (CK) max assumed under VREF – 0.18V
if measurement.
VIN (DC)
–0.3
—
VDDQ + 0.3
V
4
VIX (DC)
0.5
×
VDDQ
0.2V
0.5
×
VDDQ
0.5
×
VDDQ + 0.2V V
VID (DC)
0.36
—
VDDQ + 0.6
V
5, 6
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