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參數(shù)資料
| 型號： | EB402 |
| 英文描述： | EB402 Evaluation Board user＇s guide 7/01 |
| 中文描述： | EB402評估板用戶指南7月1日 |
| 文件頁數(shù)： | 40/84頁 |
| 文件大小： | 1014K |
| 代理商： | EB402 |
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Memory and Memory-Mapped Peripherals
3-23
The ash memory device has 19 address lines, ADDR[18:0]. The XBUS
controls ADDR[17:0], which allows it to directly access 256 kwords of
ash memory. A second 256 kword boot/instruction block is
enabled/disabled by removing/installing jumper JP15. JP15 controls the
memory’s high order address bit, A18. This design allows two versions
of the code to coexist in the ash memory; each version is in a separate
memory location, which can be accessed by installing or removing A18.
3.4.2.4 Wait States
Wait states are required when fetching instructions or data from external
memory. The number and duration of wait-states depends on the
processor clock rate (instruction cycle time). To calculate the minimum
number of wait states, use the following formula:
W = [(taccess +tsetup)/Tcycle]–1
where:
W is the number of wait states required for an external access.
t
access is the access time of the external memory device (10 ns for
SRAM and 100 ns for Flash ROM).
t
setup is the required EB402 external data set-up time (4 ns).
T
cycle is the processor instruction cycle time.
For example, assume the LSI402ZX processor clock is operating at
100 MHz. This clock frequency corresponds to
Tcycle = 1/100 MHz = 10 ns. The number of wait states for SRAM used
as external instruction memory is calculated as follows:
W = [(15 ns + 4 ns)/10 ns] – 1
W = 0.9
When W is greater than 0 but less than 1, round-up W to 1. When W is
negative, no wait states are required.
The maximum number of wait states is 128. When the LSI402ZX boots,
it defaults to the maximum number.
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