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參數(shù)資料
| 型號： | EB402 |
| 英文描述： | EB402 Evaluation Board user＇s guide 7/01 |
| 中文描述： | EB402評估板用戶指南7月1日 |
| 文件頁數(shù)： | 19/84頁 |
| 文件大?。?/td> | 1014K |
| 代理商： | EB402 |
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3-4
Hardware Overview
3.1.3 PLLBYPASS (PLL Bypass)
When PLLBYPASS is LOW (JP12 installed), CLKIN is the PLL input, and
the PLL output is the DSP Clock. When PLLBYPASS is HIGH (JP12
removed), the PLL is bypassed, and CLKIN is the DSP Clock. During
normal operation, the level of PLLBYPASS must remain constant.
3.1.4 PLLSEL[3:0] (PLL Multiplier Select)
PLLSEL[3:0] are 4 binary-coded bits that determine the value of the PLL
multiplier. If the PLL is enabled, the product of the multiplier value and
the CLKIN frequency is the frequency of the processor clock.
Set the multiplier with the rotary hex encoder, S2. The encoder has 16
positions that correspond to multipliers of 10–25. Multiplier 25 is reserved
for test. The EB402 provides a 10 MHz clock to CLKIN. Therefore, using
the on-board oscillator, the range of operating frequencies is
100–240 MHz. Table 3.1 shows the PLL multiplier select options.
The PLL multiplier should only be changed when the EB402 is not
operating because changing the multiplier causes the PLL to lose lock.
Refer to LSI402ZX Digital Signal Processor User’s Guide for more
information about PLL multiplier selection.
Table 3.1
PLL Multiplier Selections
S2 Position
PLLSEL[3:0]
CLKIN Multiplier
0
0b0000
10.0
1
0b0001
11.0
2
0b0010
12.0
3
0b0011
13.0
4
0b0100
14.0
5
0b0101
15.0
6
0b0110
16.0
7
0b0111
17.0
8
0b1000
18.0
9
0b1001
19.0
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