參數(shù)資料
型號(hào)： DZPD6710VCB
廠商： INTEL CORP
元件分類： 總線控制器
英文描述： ISA-to-PC-Card (PCMCIA) Controllers
中文描述： PCMCIA BUS CONTROLLER, PQFP144
封裝： LQFP-144
文件頁數(shù)： 110/138頁
文件大?。?/td> 723K
代理商： DZPD6710VCB
PD6710/
’
22
—
ISA-to-PC-Card (PCMCIA) Controllers
110
Datasheet
N
pres
and
N
val
are the specific selected prescaler and multiplier value from the timer set
’
s Setup,
Command, and Recovery Timing registers (see
“
Timing Registers
”
on page 84
for a description of
these registers).
From this, a PC Card cycle
’
s Setup, Command, and Recovery time for the selected timer set are
calculated as follows:
Setup time = (
S
×
Tcp
)
±
10 ns
Command time = (
C
×
Tcp
)
±
10 ns
Recovery time = (
R
×
Tcp
)
±
10 ns
When the internal synthesizer is used, the calculation of the internal clock period
Tcp
is:
Tcp
=
T
CLKP
×
4/7
where
T
CLKP
is the period of the clock supplied to the CLK input pin. An input frequency of
14.318 MHz at the CLK input pin results in an internal clock period of
Tcp
= 40 ns.
When the internal synthesizer is bypassed,
Tcp
=
T
CLKP
. An input frequency of 25 MHz in this
circumstance would also result in an internal clock period of
Tcp
= 40 ns.
The timing diagrams that follow were derived for a PD67XX using the internal synthesizer and a
14.318-MHz CLK pin input. The internal clock frequency of the PD67XX is 7/4 of this incoming
signal (
Tcp
= 40 ns). The examples are for the default values of the Timing registers for Timer Set
0, as follows:
Thus the minimum times for the default values are as follows:
Default minimum Setup time = (
S
×
Tcp
)
–
10 ns = {2
×
40 ns}
–
10 ns = 70 ns
Default minimum Command time = (
C
×
Tcp
)
–
10 ns = {7
×
40 ns}
–
10 ns = 270 ns
Default minimum Recovery time = (
R
×
Tcp
)
–
10 ns = {4
×
40 ns}
–
10 ns = 150 ns
Timing Register Name
(Timer Set 0)
Index
Value
(Default)
Resultant
N
pres
Resultant
N
val
Setup Timing 0
3Ah
01h
1
1
Command Timing 0
3Bh
06h
1
6
Recovery Timing 0
3Ch
03h
1
3
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