參數(shù)資料
型號(hào): DSPIC30F5015-30I/PT
廠商: Microchip Technology
文件頁(yè)數(shù): 61/129頁(yè)
文件大?。?/td> 0K
描述: IC DSPIC MCU/DSP 66K 64TQFP
產(chǎn)品培訓(xùn)模塊: dsPIC30F Quadrature Encoder Interface
Serial Communications using dsPIC30F CAN
Serial Communications using dsPIC30F I2C
Serial Communications using dsPIC30F SPI
Serial Communications using dsPIC30F UART
dsPIC30F 12 bit ADC - Part 2
dsPIC30F Addressing Modes - Part 1
dsPIC30F Architecture - Part 1
dsPIC30F DSP Engine & ALU
dsPIC30F Interrupts
dsPIC30F Motor Control PWM
dsPIC Timers
Asynchronous Stimulus
dsPIC30F Addressing Modes - Part 2
dsPIC30F Architecture - Part 2
dsPIC30F 12-bit ADC Part 1
標(biāo)準(zhǔn)包裝: 160
系列: dsPIC™ 30F
核心處理器: dsPIC
芯體尺寸: 16-位
速度: 30 MIP
連通性: CAN,I²C,SPI,UART/USART
外圍設(shè)備: 高級(jí)欠壓探測(cè)/復(fù)位,電機(jī)控制 PWM,QEI,POR,PWM,WDT
輸入/輸出數(shù): 52
程序存儲(chǔ)器容量: 66KB(22K x 24)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 2.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-TQFP
包裝: 托盤(pán)
產(chǎn)品目錄頁(yè)面: 651 (CN2011-ZH PDF)
配用: XLT64PT5-ND - SOCKET TRAN ICE 64MQFP/TQFP
AC164319-ND - MODULE SKT MPLAB PM3 64TQFP
DV164005-ND - KIT ICD2 SIMPLE SUIT W/USB CABLE
其它名稱: DSPIC30F501530IPT
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2008 Microchip Technology Inc.
DS70149D-page 37
dsPIC30F5015/5016
4.0
ADDRESS GENERATOR UNITS
The dsPIC DSC core contains two independent
Address Generator Units (AGU): the X AGU and Y
AGU. The Y AGU supports word-sized data reads for
the DSP MAC class of instructions only. The dsPIC DSC
AGUs support three types of data addressing:
Linear Addressing
Modulo (Circular) Addressing
Bit-Reversed Addressing
Linear and Modulo Data Addressing modes can be
applied to data space or program space. Bit-Reversed
Addressing is only applicable to data space addresses.
4.1
Instruction Addressing Modes
The addressing modes in Table 4-1 form the basis of
the addressing modes optimized to support the specific
features of individual instructions. The addressing
modes provided in the MAC class of instructions are
somewhat different from those in the other instruction
types.
4.1.1
FILE REGISTER INSTRUCTIONS
Most file register instructions use a 13-bit address field
(f) to directly address data present in the first 8192 bytes
of data memory (near data space). Most file register
instructions employ a working register W0, which is
denoted as WREG in these instructions. The destination
is typically either the same file register, or WREG (with
the exception of the MUL instruction), which writes the
result to a register or register pair. The MOV instruction
allows additional flexibility and can access the entire
data space during file register operation.
4.1.2
MCU INSTRUCTIONS
The three-operand MCU instructions are of the form:
Operand 3 = Operand 1 <function> Operand 2
where Operand 1 is always a working register (i.e., the
addressing mode can only be Register Direct), which is
referred to as Wb. Operand 2 can be a W register,
fetched from data memory, or a 5-bit literal. The result
location can be either a W register or an address
location. The following addressing modes are
supported by MCU instructions:
Register Direct
Register Indirect
Register Indirect Post-Modified
Register Indirect Pre-Modified
5-bit or 10-bit Literal
TABLE 4-1:
FUNDAMENTAL ADDRESSING MODES SUPPORTED
Note:
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual
(DS70046). For more information on the
device instruction set and programming,
refer to the “dsPIC30F/33F Programmer’s
Reference Manual” (DS70157).
Note:
Not all instructions support all the
addressing modes given above. Individual
instructions may support different subsets
of these addressing modes.
Addressing Mode
Description
File Register Direct
The address of the file register is specified explicitly.
Register Direct
The contents of a register are accessed directly.
Register Indirect
The contents of Wn forms the EA.
Register Indirect Post-Modified
The contents of Wn forms the EA. Wn is post-modified (incremented or
decremented) by a constant value.
Register Indirect Pre-Modified
Wn is pre-modified (incremented or decremented) by a signed constant value
to form the EA.
Register Indirect with Register Offset The sum of Wn and Wb forms the EA.
Register Indirect with Literal Offset
The sum of Wn and a literal forms the EA.
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