參數(shù)資料
型號： DSPIC30F5015-30I/PT
廠商： Microchip Technology
文件頁數(shù)： 129/129頁
文件大?。?/td> 0K
描述： IC DSPIC MCU/DSP 66K 64TQFP
產(chǎn)品培訓(xùn)模塊： dsPIC30F Quadrature Encoder Interface
Serial Communications using dsPIC30F CAN
Serial Communications using dsPIC30F I2C
Serial Communications using dsPIC30F SPI
Serial Communications using dsPIC30F UART
dsPIC30F 12 bit ADC - Part 2
dsPIC30F Addressing Modes - Part 1
dsPIC30F Architecture - Part 1
dsPIC30F DSP Engine & ALU
dsPIC30F Interrupts
dsPIC30F Motor Control PWM
dsPIC Timers
Asynchronous Stimulus
dsPIC30F Addressing Modes - Part 2
dsPIC30F Architecture - Part 2
dsPIC30F 12-bit ADC Part 1
標準包裝： 160
系列： dsPIC™ 30F
核心處理器： dsPIC
芯體尺寸： 16-位
速度： 30 MIP
連通性： CAN，I²C，SPI，UART/USART
外圍設(shè)備： 高級欠壓探測/復(fù)位，電機控制 PWM，QEI，POR，PWM，WDT
輸入/輸出數(shù)： 52
程序存儲器容量： 66KB（22K x 24）
程序存儲器類型： 閃存
EEPROM 大小： 1K x 8
RAM 容量： 2K x 8
電壓 - 電源 (Vcc/Vdd)： 2.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 16x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 64-TQFP
包裝： 托盤
產(chǎn)品目錄頁面： 651 (CN2011-ZH PDF)
配用： XLT64PT5-ND - SOCKET TRAN ICE 64MQFP/TQFP
AC164319-ND - MODULE SKT MPLAB PM3 64TQFP
DV164005-ND - KIT ICD2 SIMPLE SUIT W/USB CABLE
其它名稱： DSPIC30F501530IPT
2008 Microchip Technology Inc.
DS70149D-page 99
dsPIC30F5015/5016
15.4
Center-Aligned PWM
Center-aligned PWM signals are produced by the
module when the PWM time base is configured in an
Up/Down Counting mode (see Figure 15-3).
The PWM compare output is driven to the active state
when the value of the Duty Cycle register matches the
value of PTMR and the PWM time base is counting
downwards (PTDIR = 1). The PWM compare output is
driven to the inactive state when the PWM time base is
counting upwards (PTDIR = 0) and the value in the
PTMR register matches the duty cycle value.
If the value in a particular Duty Cycle register is zero,
then the output on the corresponding PWM pin will be
inactive for the entire PWM period. In addition, the out-
put on the PWM pin will be active for the entire PWM
period if the value in the Duty Cycle register is equal to
the value held in the PTPER register.
FIGURE 15-3:
CENTER-ALIGNED PWM
15.5
PWM Duty Cycle Comparison
Units
There are four 16-bit Special Function Registers
(PDC1, PDC2, PDC3 and PDC4) used to specify duty
cycle values for the PWM module.
The value in each Duty Cycle register determines the
amount of time that the PWM output is in the active
state. The Duty Cycle registers are 16 bits wide. The
LSb of a Duty Cycle register determines whether the
PWM edge occurs in the beginning. Thus, the PWM
resolution is effectively doubled.
15.5.1
DUTY CYCLE REGISTER BUFFERS
The four PWM Duty Cycle registers are double-buffered
to allow glitchless updates of the PWM outputs. For each
duty cycle, there is a Duty Cycle register that is accessi-
ble by the user, and a second Duty Cycle register that
holds the actual compare value used in the present
PWM period.
For edge-aligned PWM output, a new duty cycle value
will be updated whenever a match with the PTPER reg-
ister occurs and PTMR is reset. The contents of the
duty cycle buffers are automatically loaded into the
Duty Cycle registers when the PWM time base is dis-
abled (PTEN = 0) and the UDIS bit is cleared in
PWMCON2.
When the PWM time base is in the Up/Down Counting
mode, new duty cycle values are updated when the
value of the PTMR register is zero and the PWM time
base begins to count upwards. The contents of the duty
cycle buffers are automatically loaded into the Duty
Cycle registers when the PWM time base is disabled
(PTEN = 0).
When the PWM time base is in the Up/Down Counting
mode with double updates, new duty cycle values are
updated when the value of the PTMR register is zero,
and when the value of the PTMR register matches the
value in the PTPER register. The contents of the duty
cycle buffers are automatically loaded into the Duty
Cycle registers when the PWM time base is disabled
(PTEN = 0).
15.5.2
DUTY CYCLE IMMEDIATE
UPDATES
When the Immediate Update Enable bit is set (IUE = 1),
any write to the Duty Cycle registers updates the new
duty cycle value immediately. This feature gives the
option to the user to allow immediate updates of the
active PWM Duty Cycle registers instead of waiting for
the end of the current time base period. System stabil-
ity is improved in closed-loop servo applications by
reducing the delay between system observation and
the issuance of system corrective commands when
immediate updates are enabled.
If the PWM output is active at the time the new duty
cycle is written, and the new duty cycle is less than the
current time base value, the PWM pulse width is
shortened.
If the PWM output is active at the time the new duty
cycle is written, and the new duty cycle is greater than
the current time base value, the PWM pulse width is
lengthened.
If the PWM output is inactive at the time the new duty
cycle is written, and the new duty cycle is greater than
the current time base value, the PWM output becomes
active immediately and remains active for the new
written duty cycle value.
0
PTPER
PTMR
Value
Period
Period/2
Duty
Cycle
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