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| 型號(hào)： | DSPIC30F5015-30I/PT |
| 廠商： | Microchip Technology |
| 文件頁(yè)數(shù)： | 34/129頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DSPIC MCU/DSP 66K 64TQFP |
| 產(chǎn)品培訓(xùn)模塊： | dsPIC30F Quadrature Encoder Interface Serial Communications using dsPIC30F CAN Serial Communications using dsPIC30F I2C Serial Communications using dsPIC30F SPI Serial Communications using dsPIC30F UART dsPIC30F 12 bit ADC - Part 2 dsPIC30F Addressing Modes - Part 1 dsPIC30F Architecture - Part 1 dsPIC30F DSP Engine & ALU dsPIC30F Interrupts dsPIC30F Motor Control PWM dsPIC Timers Asynchronous Stimulus dsPIC30F Addressing Modes - Part 2 dsPIC30F Architecture - Part 2 dsPIC30F 12-bit ADC Part 1 |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 系列： | dsPIC™ 30F |
| 核心處理器： | dsPIC |
| 芯體尺寸： | 16-位 |
| 速度： | 30 MIP |
| 連通性： | CAN，I²C，SPI，UART/USART |
| 外圍設(shè)備： | 高級(jí)欠壓探測(cè)/復(fù)位，電機(jī)控制 PWM，QEI，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 52 |
| 程序存儲(chǔ)器容量： | 66KB（22K x 24） |
| 程序存儲(chǔ)器類(lèi)型： | 閃存 |
| EEPROM 大?。?/td> | 1K x 8 |
| RAM 容量： | 2K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.5 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 16x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 64-TQFP |
| 包裝： | 托盤(pán) |
| 產(chǎn)品目錄頁(yè)面： | 651 (CN2011-ZH PDF) |
| 配用： | XLT64PT5-ND - SOCKET TRAN ICE 64MQFP/TQFP AC164319-ND - MODULE SKT MPLAB PM3 64TQFP DV164005-ND - KIT ICD2 SIMPLE SUIT W/USB CABLE |
| 其它名稱： | DSPIC30F501530IPT |
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2008 Microchip Technology Inc.
DS70149D-page 129
dsPIC30F5015/5016
Receive Error Interrupts
A receive error interrupt will be indicated by the ERRIF
bit. This bit shows that an error condition occurred. The
source of the error can be determined by checking the
bits in the CAN Interrupt Status register, CiINTF.
Invalid message received
If any type of error occurred during reception of the last
message, an error will be indicated by the IVRIF bit.
Receiver overrun
The RXnOVR bit indicates that an overrun condition
occurred.
Receiver warning
The RXWAR bit indicates that the Receive Error Coun-
ter (RERRCNT<7:0>) has reached the warning limit of
96.
Receiver error passive
The RXEP bit indicates that the Receive Error Counter
has exceeded the error passive limit of 127 and the
module has gone into Error Passive state.
19.5
Message Transmission
19.5.1
TRANSMIT BUFFERS
The CAN module has three transmit buffers. Each of
the three buffers occupies 14 bytes of data. Eight of the
bytes are the maximum 8 bytes of the transmitted mes-
sage. Five bytes hold the standard and extended
identifiers and other message arbitration information.
19.5.2
TRANSMIT MESSAGE PRIORITY
Transmit priority is a prioritization within each node of the
pending transmittable messages. There are 4 levels of
transmit priority. If TXPRI<1:0> (CiTXnCON<1:0>, where
n = 0, 1 or 2 represents a particular transmit buffer) for a
particular message buffer is set to ‘11’, that buffer has the
highest priority. If TXPRI<1:0> for a particular message
buffer is set to ‘10’ or ‘01’, that buffer has an intermediate
priority. If TXPRI<1:0> for a particular message buffer is
‘00’, that buffer has the lowest priority.
19.5.3
TRANSMISSION SEQUENCE
To initiate transmission of the message, the TXREQ bit
(CiTXnCON<3>) must be set. The CAN bus module
resolves any timing conflicts between setting of the
TXREQ bit and the Start-of-Frame (SOF), ensuring
that if the priority was changed, it is resolved correctly
before the SOF occurs. When TXREQ is set, the
TXABT (CiTXnCON<6>), TXLARB (CiTXnCON<5>)
and
TXERR
(CiTXnCON<4>)
flag
bits
are
automatically cleared.
Setting the TXREQ bit simply flags a message buffer as
enqueued for transmission. When the module detects
an available bus, it begins transmitting the message
which has been determined to have the highest priority.
If the transmission completes successfully on the first
attempt, the TXREQ bit is cleared automatically and an
interrupt is generated if TXIE was set.
If the message transmission fails, one of the error
condition flags will be set and the TXREQ bit will
remain set indicating that the message is still pending
for transmission. If the message encountered an error
condition during the transmission attempt, the TXERR
bit will be set and the error condition may cause an
interrupt. If the message loses arbitration during the
transmission attempt, the TXLARB bit is set. No
interrupt is generated to signal the loss of arbitration.
19.5.4
ABORTING MESSAGE
TRANSMISSION
The system can also abort a message by clearing the
TXREQ bit associated with each message buffer. Set-
ting the ABAT bit (CiCTRL<12>) will request an abort of
all pending messages. If the message has not yet
started transmission, or if the message started but is
interrupted by loss of arbitration or an error, the abort
will be processed. The abort is indicated when the
module sets the TXABT bit and the TXnIF flag is not
automatically set.
19.5.5
TRANSMISSION ERRORS
The CAN module will detect the following transmission
errors:
Acknowledge Error
Form Error
Bit Error
These transmission errors will not necessarily generate
an interrupt, but are indicated by the transmission error
counter. However, each of these errors will cause the
transmission error counter to be incremented by one.
Once the value of the error counter exceeds the value
of 96, the ERRIF (CiINTF<5>) and the TXWAR bit
(CiINTF<10>) are set. Once the value of the error
counter exceeds the value of 96, an interrupt is
generated and the TXWAR bit in the Error Flag register
is set.
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