參數(shù)資料
型號(hào)： DSPIC30F5015-30I/PT
廠商： Microchip Technology
文件頁數(shù)： 128/129頁
文件大?。?/td> 0K
描述： IC DSPIC MCU/DSP 66K 64TQFP
產(chǎn)品培訓(xùn)模塊： dsPIC30F Quadrature Encoder Interface
Serial Communications using dsPIC30F CAN
Serial Communications using dsPIC30F I2C
Serial Communications using dsPIC30F SPI
Serial Communications using dsPIC30F UART
dsPIC30F 12 bit ADC - Part 2
dsPIC30F Addressing Modes - Part 1
dsPIC30F Architecture - Part 1
dsPIC30F DSP Engine & ALU
dsPIC30F Interrupts
dsPIC30F Motor Control PWM
dsPIC Timers
Asynchronous Stimulus
dsPIC30F Addressing Modes - Part 2
dsPIC30F Architecture - Part 2
dsPIC30F 12-bit ADC Part 1
標(biāo)準(zhǔn)包裝： 160
系列： dsPIC™ 30F
核心處理器： dsPIC
芯體尺寸： 16-位
速度： 30 MIP
連通性： CAN，I²C，SPI，UART/USART
外圍設(shè)備： 高級(jí)欠壓探測(cè)/復(fù)位，電機(jī)控制 PWM，QEI，POR，PWM，WDT
輸入/輸出數(shù)： 52
程序存儲(chǔ)器容量： 66KB（22K x 24）
程序存儲(chǔ)器類型： 閃存
EEPROM 大小： 1K x 8
RAM 容量： 2K x 8
電壓 - 電源 (Vcc/Vdd)： 2.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 16x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 64-TQFP
包裝： 托盤
產(chǎn)品目錄頁面： 651 (CN2011-ZH PDF)
配用： XLT64PT5-ND - SOCKET TRAN ICE 64MQFP/TQFP
AC164319-ND - MODULE SKT MPLAB PM3 64TQFP
DV164005-ND - KIT ICD2 SIMPLE SUIT W/USB CABLE
其它名稱： DSPIC30F501530IPT
dsPIC30F5015/5016
DS70149D-page 98
2008 Microchip Technology Inc.
15.1.4
DOUBLE UPDATE MODE
In the Double Update mode (PTMOD<1:0> = 11), an
interrupt event is generated each time the PTMR
register is equal to zero, as well as each time a period
match occurs. The postscaler selection bits have no
effect in this mode of the timer.
The Double Update mode provides two additional
functions to the user. First, the control loop bandwidth
is doubled because the PWM duty cycles can be
updated, twice per period. Second, asymmetrical
center-aligned PWM waveforms can be generated,
which are useful for minimizing output waveform
distortion in certain motor control applications.
15.1.5
PWM TIME BASE PRESCALER
The input clock to PTMR (FOSC/4), has prescaler
options of 1:1, 1:4, 1:16, or 1:64, selected by control
bits PTCKPS<1:0> in the PTCON SFR. The prescaler
counter is cleared when any of the following occurs:
a write to the PTMR register
a write to the PTCON register
any device Reset
PTMR is not cleared when PTCON is written.
15.1.6
PWM TIME BASE POSTSCALER
The match output of PTMR can optionally be
post-scaled through a 4-bit postscaler (which gives a
1:1 to 1:16 scaling).
The postscaler counter is cleared when any of the
following occurs:
a write to the PTMR register
a write to the PTCON register
any device Reset
The PTMR register is not cleared when PTCON is written.
15.2
PWM Period
PTPER is a 15-bit register and is used to set the counting
period for the PWM time base. PTPER is a
double-buffered register. The PTPER buffer contents are
loaded into the PTPER register at the following instants:
Free-Running and Single-Shot modes: When the
PTMR register is reset to zero after a match with
the PTPER register.
Up/Down Counting modes: When the PTMR
register is zero.
The value held in the PTPER buffer is automatically
loaded into the PTPER register when the PWM time
base is disabled (PTEN = 0).
The
PWM
period
can
be
determined
using
EQUATION 15-1:
PWM PERIOD
If the PWM time base is configured for one of the
Up/Down Count modes, the PWM period is given by
EQUATION 15-2:
PWM PERIOD (UP/DOWN
MODE)
The maximum resolution (in bits) for a given device
oscillator and PWM frequency can be determined using
EQUATION 15-3:
PWM RESOLUTION
15.3
Edge-Aligned PWM
Edge-aligned PWM signals are produced by the module
when the PWM time base is in the Free-Running or
Single-Shot mode. For edge-aligned PWM outputs, the
output has a period specified by the value in PTPER
and a duty cycle specified by the appropriate Duty Cycle
register (see Figure 15-2). The PWM output is driven
active at the beginning of the period (PTMR = 0) and is
driven inactive when the value in the Duty Cycle register
matches PTMR.
If the value in a particular Duty Cycle register is zero,
then the output on the corresponding PWM pin will be
inactive for the entire PWM period. In addition, the
output on the PWM pin will be active for the entire
PWM period if the value in the Duty Cycle register is
greater than the value held in the PTPER register.
FIGURE 15-2:
EDGE-ALIGNED PWM
Note:
Programming a value of 0x0001 in the
Period
register
could
generate
a
continuous interrupt pulse and hence,
must be avoided.
TPWM =
TCY
(PTPER + 1)
(PTMR Prescale Value)
TPWM =
2 TCY (PTPER + 1)
(PTMR Prescale Value)
Resolution =
log (2
TPWM/TCY)
log (2)
Period
Duty Cycle
0
PTPER
PTMR
Value
New Duty Cycle Latched
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