參數(shù)資料
型號: DSP56858FVE
廠商: Freescale Semiconductor
文件頁數(shù): 25/64頁
文件大小: 0K
描述: IC DSP 16BIT 120MHZ 144-LQFP
標(biāo)準(zhǔn)包裝: 60
系列: 568xx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 120MHz
連通性: EBI/EMI,SCI,SPI,SSI
外圍設(shè)備: DMA,POR,WDT
輸入/輸出數(shù): 47
程序存儲器容量: 80KB(40K x 16)
程序存儲器類型: SRAM
RAM 容量: 24K x 16
電壓 - 電源 (Vcc/Vdd): 1.62 V ~ 1.98 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 144-LQFP
包裝: 托盤
External Memory Interface Timing
56858 Technical Data, Rev. 6
Freescale Semiconductor
31
M Fixed portion of a clock period inherent in the design. This number is adjusted to account for possible
clock duty cycle derating.
W the sum of the applicable wait state controls. See the “Wait State Controls” column of Table 4-7 for
the applicable controls for each parameter. See the EMI chapter of the 83x Peripheral Manual for
details of what each wait state field controls.
Some of the parameters contain two sets of numbers. These parameters have two different paths and clock edges
that must be considered. Check both sets of numbers and use the smaller result. The appropriate entry may change
if the operating frequency of the part changes.
The timing of write cycles is different when WWS = 0 than when WWS > 0. Therefore, some parameters contain
two sets of numbers to account for this difference. The “Wait States Configuration” column of Table 4-7 should be
used to make the appropriate selection.
Figure 4-10 External Memory Interface Timing
tDRD
tRDD
tAD
tDOH
tDOS
tDWR
tRDWR
tWAC
tWRRD
tWR
tAWR
tWRWR
tARDD
tRDA
tRDRD
tRD
tARDA
Data Out
Data In
A0-Axx,CS
RD
WR
D0-D15
Note: During read-modify-write instructions and internal instructions, the address lines do not change state.
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