I
參數(shù)資料
型號： DSP56858FVE
廠商： Freescale Semiconductor
文件頁數(shù)： 18/64頁
文件大?。?/td> 0K
描述： IC DSP 16BIT 120MHZ 144-LQFP
標準包裝： 60
系列： 568xx
核心處理器： 56800E
芯體尺寸： 16-位
速度： 120MHz
連通性： EBI/EMI，SCI，SPI，SSI
外圍設(shè)備： DMA，POR，WDT
輸入/輸出數(shù)： 47
程序存儲器容量： 80KB（40K x 16）
程序存儲器類型： SRAM
RAM 容量： 24K x 16
電壓 - 電源 (Vcc/Vdd)： 1.62 V ~ 1.98 V
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 144-LQFP
包裝： 托盤
DC Electrical Characteristics
56858 Technical Data, Rev. 6
Freescale Semiconductor
25
Input current low (pullups disabled)
IIL
-1
—
1
μA
Input current high (pullups disabled)
IIH
-1
—
1
μA
Output tri-state current low
IOZL
-10
—
10
μA
Output tri-state current high
IOZH
-10
—
10
μA
Output High Voltage
VOH
VDDIO – 0.7
—
V
Output Low Voltage
VOL
——
0.4
V
Output High Current
IOH
8—
16
mA
Output Low Current
IOL
8—
16
mA
Input capacitance
CIN
—8
—
pF
Output capacitance
COUT
—12
—
pF
VDD supply current (Core logic, memories, peripherals)
Run 1
Deep Stop2
Light Stop3
IDD4
—
70
0.05
5
110
10
14
mA
VDDIO supply current (I/O circuity)
Run5
Deep Stop2
IDDIO
—40
0
50
1.5
mA
VDDA supply current (analog circuity)
Deep Stop2
IDDA
—60
120
μA
Low Voltage Interrupt6
VEI
—
2.5
2.85
V
Low Voltage Interrupt Recovery Hysteresis
VEIH
—50
—
mV
Power on Reset7
POR
—
1.5
2.0
V
Note:
Run (operating) IDD measured using external square wave clock source (fosc = 4MHz) into XTAL. All inputs 0.2V from rail;
no DC loads; outputs unloaded. All ports configured as inputs; measured with all modules enabled. PLL set to 240MHz out.
1. Running Core, performing 50% NOP and 50% FIR. Clock at 120 MHz.
2. Deep Stop Mode - Operation frequency = 4 MHz, PLL set to 4 MHz, crystal oscillator and time of day module operating.
3. Light Stop Mode - Operation frequency = 120 MHz, PLL set to 240 MHz, crystal oscillator and time of day module operating.
4. IDD includes current for core logic, internal memories, and all internal peripheral logic circuitry.
5. Running core and performing external memory access. Clock at 120 MHz.
6. When VDD drops below VEI max value, an interrupt is generated.
7. Power-on reset occurs whenever the digital supply drops below 1.8V. While power is ramping up, this signal remains active
for as long as the internal 2.5V is below 1.8V no matter how long the ramp up rate is. The internally regulated voltage is
typically 100 mV less than VDD during ramp up until 2.5V is reached, at which time it self-regulates.
Table 4-4 DC Electrical Characteristics (Continued)
Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz
Characteristic
Symbol
Min
Typ
Max
Unit
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