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| 型號： | DSP56857BUE |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 10/53頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP 16BIT 120MHZ 100-LQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | 568xx |
| 核心處理器： | 56800E |
| 芯體尺寸： | 16-位 |
| 速度： | 120MHz |
| 連通性： | SCI，SPI，SSI |
| 外圍設(shè)備： | DMA，POR，WDT |
| 輸入/輸出數(shù)： | 47 |
| 程序存儲器容量： | 80KB（40K x 16） |
| 程序存儲器類型： | SRAM |
| RAM 容量： | 24K x 16 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.62 V ~ 1.98 V |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 100-LQFP |
| 包裝： | 托盤 |
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56857 Technical Data, Rev. 6
18
Freescale Semiconductor
70
SC11
GPIOD4
Input/Output
Input/Output
ESSI Serial Control Pin 1 (SC11)—The function of this pin is determined
by the selection of either synchronous or asynchronous mode. For
asynchronous mode, this pin is the receiver frame sync I/O. For
synchronous mode, this pin is used either for transmitter2 output or for
serial I/O flag 1.
Port D GPIO (4)—This pin is a General Purpose I/O (GPIO) pin when the
ESSI is not in use.
71
SC12
GPIOD5
Input/Output
Input/Output
ESSI Serial Control Pin 2 (SC12)—This pin is used for frame sync I/O.
SC02 is the frame sync for both the transmitter and receiver in
synchronous mode and for the transmitter only in asynchronous mode.
When configured as an output, this pin is the internally generated frame
sync signal. When configured as an input, this pin receives an external
frame sync signal for the transmitter (and the receiver in synchronous
operation).
Port D GPIO (5)—This pin is a General Purpose I/O (GPIO) pin when the
ESSI is not in use.
1MISO
GPIOF0
Input/Output
Input/Output
SPI Master In/Slave Out (MISO)—This serial data pin is an input to a
master device and an output from a slave device. The MISO line of a
slave device is placed in the high-impedance state if the slave device is
not selected. The driver on this pin can be configured as an open-drain
driver by the SPI’s Wired-OR mode (WOM) bit when this pin is configured
for SPI operation.
Port F GPIO (0)—This pin is a General Purpose I/O (GPIO) pin that can
individually be programmed as input or output pin.
2MOSI
GPIOF1
Input/
Output (Z)
Input/Output
SPI Master Out/Slave In (MOSI)—This serial data pin is an output from a
master device and an input to a slave device. The master device places
data on the MOSI line a half-cycle before the clock edge that the slave
device uses to latch the data. The driver on this pin can be configured as
an open-drain driver by the SPI’s WOM bit when this pin is configured for
SPI operation.
Port F GPIO (1)—This pin is a General Purpose I/O (GPIO) pin that can
be individually programmed as input or output pin.
Table 3-1 56857 Signal and Package Information for the 100-pin LQFP (Continued)
Pin No.
Signal Name
Type
Description
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