參數(shù)資料
型號： DSP56852VFE
廠商： Freescale Semiconductor
文件頁數(shù)： 5/48頁
文件大?。?/td> 0K
描述： IC DSP 16BIT 120MHZ 81-MAPBGA
標準包裝： 348
系列： 568xx
核心處理器： 56800E
芯體尺寸： 16-位
速度： 120MHz
連通性： EBI/EMI，SCI，SPI，SSI
外圍設備： POR，WDT
輸入/輸出數(shù)： 11
程序存儲器容量： 12KB（6K x 16）
程序存儲器類型： SRAM
RAM 容量： 4K x 16
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 3.3 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 81-LFBGA
包裝： 托盤
Introduction
56852 Technical Data, Rev. 8
Freescale Semiconductor
13
C4
MISO
GPIOC4
SRCK
Input/Output
Input/Output
SPI Master In/Slave Out (MISO)—This serial data pin is an input to a
master device and an output from a slave device. The MISO line of a
slave device is placed in the high-impedance state if the slave device is
not selected.
Port C GPIO (4)—This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as input or output pin.
SSI Serial Receive Clock (SRCK)—This bidirectional pin provides the
serial bit rate clock for the receive section of the SSI. The clock signal
can be continuous or gated.
C5
MOSI
GPIOC5
SRFS
Input/
Output (Z)
Input/Output
SPI Master Out/Slave In (MOSI)—This serial data pin is an output from
a master device and an input to a slave device. The master device
places data on the MOSI line a half-cycle before the clock edge that the
slave device uses to latch the data.
Port C GPIO (5)—This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as input or output pin.
SSI Serial Receive Frame Sync (SRFS)— This bidirectional pin is
used to count the number of words in a frame while receiving. A
programmable frame rate divider and a word length divider are used for
frame rate sync signal generation.
A1
IRQA
Input
External Interrupt Request A (IRQA)—The IRQA Schmitt trigger input
is a synchronized external interrupt request that indicates that an
external device is requesting service. It can be programmed to be
level-sensitive or negative-edge- triggered.
C2
IRQB
Input
External Interrupt Request B (IRQB)—The IRQB Schmitt trigger input
is an external interrupt request that indicates that an external device is
requesting service. It can be programmed to be level-sensitive or
negative-edge-triggered.
A6
EXTAL
Input
External Crystal Oscillator Input (EXTAL)—This input should be
connected to an external crystal. If an external clock source other than a
crystal oscillator is used, EXTAL must be tied off.
A7
XTAL
Input/Output
Crystal Oscillator Output (XTAL)—This output connects the internal
crystal oscillator output to an external crystal. If an external clock source
other than a crystal oscillator is used, XTAL must be used as the input.
Table 3-1. 56852 Signal and Package Information for the 81-pin MAPBGA (Continued)
Pin No.
Signal Name
Type
Description
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