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參數(shù)資料
| 型號： | DSP56852VFE |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 19/48頁 |
| 文件大小： | 0K |
| 描述： | IC DSP 16BIT 120MHZ 81-MAPBGA |
| 標(biāo)準(zhǔn)包裝： | 348 |
| 系列： | 568xx |
| 核心處理器： | 56800E |
| 芯體尺寸： | 16-位 |
| 速度： | 120MHz |
| 連通性： | EBI/EMI，SCI，SPI，SSI |
| 外圍設(shè)備： | POR，WDT |
| 輸入/輸出數(shù)： | 11 |
| 程序存儲器容量： | 12KB（6K x 16） |
| 程序存儲器類型： | SRAM |
| RAM 容量： | 4K x 16 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.8 V ~ 3.3 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 81-LFBGA |
| 包裝： | 托盤 |
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56852 Technical Data, Rev. 8
26
Freescale Semiconductor
4.7 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Table 4-8 Reset, Stop, Wait, Mode Select, and Interrupt Timing 1, 2
Operating Conditions: VSS = VSSIO = VSSA = 0V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL < 50pF, fop = 120MHz
1. In the formulas, T = clock cycle. For fop = 120MHz operation and fipb = 60MHz, T = 8.33ns.
2. Parameters listed are guaranteed by design.
Characteristic
Symbol
Min
Max
Unit
See Figure
RESET Assertion to Address, Data and Control Signals
High Impedance
tRAZ
—
11
ns
Minimum RESET Assertion Duration3
3. At reset, the PLL is disabled and bypassed. The part is then put into run mode and tclk assumes the period of the source clock, txtal,
textal or tosc.
tRA
30
—
ns
RESET Deassertion to First External Address Output
tRDA
—
120T
ns
Edge-sensitive Interrupt Request Width
tIRW
1T + 3
—
ns
IRQA, IRQB Assertion to External Data Memory Access
Out Valid, caused by first instruction execution in the
interrupt service routine
tIDM
18T
—
ns
tIDM -FAST
14T
—
IRQA, IRQB Assertion to General Purpose Output Valid,
caused by first instruction execution in the interrupt
service routine
tIG
18T
—
ns
tIG -FAST
14T
—
IRQA Low to First Valid Interrupt Vector Address Out
recovery from Wait State4
4. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is not
the minimum required so that the IRQA interrupt is accepted.
tIRI
22T
—
ns
tIRI -FAST
18T
—
Delay from IRQA Assertion (exiting Stop) to External
Data Memory5
5. The interrupt instruction fetch is visible on the pins only in Mode 3.
tIW
1.5T
—
ns
Delay from IRQA Assertion (exiting Wait) to External
Data Memory
Fast6
Normal7
6. Fast stop mode:
Fast stop recovery applies when external clocking is in use (direct clocking to XTAL) or when fast stop mode recovery is requested
(OMR bit 6 is set to 1). In both cases the PLL and the master clock are unaffected by stop mode entry. Recovery takes one less cycle
and tclk will continue same value it had before stop mode was entered.
7. Normal stop mode:
As a power saving feature, normal stop mode disables and bypasses the PLL. Stop mode will then shut down the master clock,
recovery will take an extra cycle (to restart the clock), and tclk will resume at the input clock source rate.
tIF
18T
22ET
—
ns
RSTO pulse width8
normal operation
internal reset mode
8. ET = External Clock period, For an external crystal frequency of 8MHz, ET=125 ns.
tRSTO
128ET
8ET
—
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