參數(shù)資料
型號(hào): DSP56852VFE
廠(chǎng)商: Freescale Semiconductor
文件頁(yè)數(shù): 46/48頁(yè)
文件大?。?/td> 0K
描述: IC DSP 16BIT 120MHZ 81-MAPBGA
標(biāo)準(zhǔn)包裝: 348
系列: 568xx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 120MHz
連通性: EBI/EMI,SCI,SPI,SSI
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 11
程序存儲(chǔ)器容量: 12KB(6K x 16)
程序存儲(chǔ)器類(lèi)型: SRAM
RAM 容量: 4K x 16
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.3 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 81-LFBGA
包裝: 托盤(pán)
Introduction
56852 Technical Data, Rev. 8
Freescale Semiconductor
7
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56852 are organized into functional groups, as shown in Table 2-1 and
as illustrated in Figure 2-1. In Table 3-1, each table row describes the package pin and the signal or
signals present.
1. VDD = VDD CORE, VSS = VSS CORE, VDDIO= VDD IO, VSSIO = VSS IO, VDDA = VDD ANA, VSSA = VSS ANA
2. CLKOUT is muxed Address pin A20.
3. Four Address pins are multiplexed with the timer, CS3 and CLKOUT pins.
4. CS3 is multiplexed with external Address Bus pin A19.
5. Mode pins are multiplexed with External Data pins D13-D15 like A17and A18.
6. Four of these pins are multiplexed with SSI.
7. Two of these pins are multiplexed with 2 bits of the External Address Bus A17and A18.
Table 2-1 Functional Group Pin Allocations
Functional Group
Number of Pins
Power (VDD, VDDIO, or VDDA)
101
Ground (VSS, VSSIO,or VSSA)
101
Phase Lock Loop (PLL) and Clock
22
External Bus Signals
393
External Chip Select*
34
Interrupt and Program Control
35
Synchronous Serial Interface (SSI) Port*
6
Serial Communications Interface (SCI) Port*
2
Serial Peripheral Interface (SPI) Port
06
Quad Timer Module Port
07
JTAG/Enhanced On-Chip Emulation (EOnCE)
6
*Alternately, GPIO pins
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