參數(shù)資料
型號: DSP56852VFE
廠商: Freescale Semiconductor
文件頁數(shù): 14/48頁
文件大小: 0K
描述: IC DSP 16BIT 120MHZ 81-MAPBGA
標準包裝: 348
系列: 568xx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 120MHz
連通性: EBI/EMI,SCI,SPI,SSI
外圍設備: POR,WDT
輸入/輸出數(shù): 11
程序存儲器容量: 12KB(6K x 16)
程序存儲器類型: SRAM
RAM 容量: 4K x 16
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.3 V
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 81-LFBGA
包裝: 托盤
External Clock Operation
56852 Technical Data, Rev. 8
Freescale Semiconductor
21
Figure 4-5 shows the definitions of the following signal states:
Active state, when a bus or signal is driven, and enters a low impedance state
Tri-stated, when a bus or signal is placed in a high impedance state
Data Valid state, when a signal level has reached VOL or VOH
Data Invalid state, when a signal level is in transition between VOL and VOH
Figure 4-5 Signal States
4.5 External Clock Operation
The 56852 system clock can be derived from a crystal or an external system clock signal. To generate a
reference frequency using the internal oscillator, a reference crystal must be connected between the
EXTAL and XTAL pins.
4.5.1
Crystal Oscillator for Use with PLL
The internal oscillator is designed to interface with a parallel-resonant crystal resonator in the frequency
range specified for the external crystal in Table 4-6. In Figure 4-6 a typical crystal oscillator circuit is
shown. Follow the crystal supplier’s recommendations when selecting a crystal, because crystal
parameters determine the component values required to provide maximum stability and reliable start-up.
The crystal and associated components should be mounted as close as possible to the EXTAL and XTAL
pins to minimize output distortion and start-up stabilization time.
Figure 4-6 Crystal Oscillator
Data Invalid State
Data1
Data2 Valid
Data
Tri-stated
Data3 Valid
Data2
Data3
Data1 Valid
Data Active
Sample External Crystal
Parameters:
Rz = 10MΩ
TOD_SEL bit in CGM may be set to
0 or 1. 0 is recommended.
Crystal Frequency = 2–4MHz (optimized for 4MHz)
EXTAL XTAL
Rz
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