Characteris" />
參數(shù)資料
型號: DSP56303AG100B1
廠商: Freescale Semiconductor
文件頁數(shù): 61/108頁
文件大?。?/td> 0K
描述: IC DSP 24BIT 100MHZ 144-LQFP
標(biāo)準(zhǔn)包裝: 300
系列: DSP563xx
類型: 定點(diǎn)
接口: 主機(jī)接口,SSI,SCI
時鐘速率: 100MHz
非易失內(nèi)存: ROM(576 B)
芯片上RAM: 24kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 3.30V
工作溫度: -40°C ~ 100°C
安裝類型: 表面貼裝
封裝/外殼: 144-LQFP
供應(yīng)商設(shè)備封裝: 144-LQFP(20x20)
包裝: 托盤
DSP56303 Technical Data, Rev. 11
2-36
Freescale Semiconductor
Specifications
2.5.7
SCI Timing
Table 2-17.
SCI Timings
No.
Characteristics1
Symbol
Expression
100 MHz
Unit
Min
Max
400
Synchronous clock cycle
tSCC
2
8
× T
C
53.3
ns
401
Clock low period
tSCC/2 10.0
16.7
ns
402
Clock high period
tSCC/2 10.0
16.7
ns
403
Output data setup to clock falling edge (internal
clock)
tSCC/4 + 0.5 × TC 17.0
8.0
ns
404
Output data hold after clock rising edge (internal
clock)
tSCC/4 0.5 × TC
15.0
ns
405
Input data setup time before clock rising edge
(internal clock)
tSCC/4 + 0.5 × TC + 25.0
50.0
ns
406
Input data not valid before clock rising edge
(internal clock)
tSCC/4 + 0.5 × TC 5.5
19.5
ns
407
Clock falling edge to output data valid (external
clock)
—32.0
ns
408
Output data hold after clock rising edge (external
clock)
TC + 8.0
18.0
ns
409
Input data setup time before clock rising edge
(external clock)
0.0
ns
410
Input data hold time after clock rising edge
(external clock)
9.0
ns
411
Asynchronous clock cycle
tACC
3
64
× TC
640.0
ns
412
Clock low period
tACC/2 10.0
310.0
ns
413
Clock high period
tACC/2 10.0
310.0
ns
414
Output data setup to clock rising edge (internal
clock)
tACC/2 30.0
290.0
ns
415
Output data hold after clock rising edge (internal
clock)
tACC/2 30.0
290.0
ns
Notes:
1.
VCC = 3.3 V ± 0.3 V; TJ = 40°C to +100 °C, CL = 50 pF.
2.
tSCC = synchronous clock cycle time (for internal clock, tSCC is determined by the SCI clock control register and TC).
3.
tACC = asynchronous clock cycle time; value given for 1X Clock mode (for internal clock, tACC is determined by the SCI clock
control register and TC).
4.
An expression is used to compute the number listed as the minimum or maximum value as appropriate.
相關(guān)PDF資料
PDF描述
KMSC7119VF1200 DSP 16BIT W/DDR CTRLR 400-MAPBGA
VI-21P-EU CONVERTER MOD DC/DC 13.8V 200W
VI-21N-EU CONVERTER MOD DC/DC 18.5V 200W
KMSC7119VM1200 DSP 16BIT W/DDR CTRLR 400-MAPBGA
KMSC7118VF1200 DSP 16BIT W/DDR CTRLR 400-MAPBGA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DSP56303AG100R2 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 24 BIT DSP RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
DSP56303EVM 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC DSP56303 Eval Kit RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
DSP56303EVMCL 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP56303EVM DSP56303EVM Kit Contents List
DSP56303EVMUM 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP56303 EVM Users Manual
DSP56303PV100 制造商:Freescale Semiconductor 功能描述:Digital Signal Processor, 24 Bit, 144 Pin, Plastic, QFP