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參數(shù)資料
| 型號： | DS89C450 |
| 英文描述： | Ultra-High-Speed Flash Microcontrollers |
| 中文描述： | 超高速閃存微控制器 |
| 文件頁數(shù)： | 41/48頁 |
| 文件大小： | 934K |
| 代理商： | DS89C450 |
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DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers
41 of 48
Watchdog Timer
The watchdog timer functions as the source of both the watchdog interrupt and the watchdog reset. When the clock
divider is set to 10b, the interrupt timeout has a default divide ratio of 2
of the crystal oscillator clock, with the
watchdog reset set to time out 512 system clock cycles later. This results in a 33MHz crystal oscillator producing
an interrupt timeout every 3.9718ms, followed 15.5μs later by a watchdog reset. The watchdog timer is reset to the
default divide ratio following any reset. Using the WD0 and WD1 bits in the clock control (CKCON.6 and 7) register,
other divide ratios can be selected for longer watchdog interrupt periods.
Table 14
summarizes the watchdog bits
settings and the timeout values.
Note:
All watchdog timer reset timeouts follow the programmed interrupt timeouts
by 512 system clock cycles, which equates to varying numbers of oscillator cycles depending on the clock divide
(CD1:0) and crystal multiplier settings.
Table 14. Watchdog Timeout Value (In Number of Oscillator Clocks)
WATCHDOG INTERRUPT TIMEOUT
WATCHDOG RESET TIMEOUT
4X/
2X
CD1:0
WD1:0 = 00 WD1:0 = 01 WD1:0 = 10 WD1:0 = 11
WD1:0 = 00
WD1:0 = 01
WD1:0 = 10
WD1:0 = 11
1
00
2
15
2
18
2
21
2
24
2
15
+ 128
2
18
+ 128
2
21
+ 128
2
24
+ 128
0
00
2
16
2
19
2
22
2
25
2
16
+ 256
2
19
+ 256
2
22
+ 256
2
25
+ 256
x
01
2
17
2
20
2
23
2
26
2
17
+ 512
2
20
+ 512
2
23
+ 512
2
26
+ 512
x
10
2
17
2
20
2
23
2
26
2
17
+ 512
2
20
+ 512
2
23
+ 512
2
26
+ 512
x
11
2
27
2
30
2
33
2
36
2
27
+ 524,288
2
30
+ 524,288
2
33
+ 524,288
2
36
+ 524,288
A watchdog control (WDCON) SFR is used for programming the functions. EWT (WDCON.1) is the enable for the
watchdog timer-reset function and RWT (WDCON.0) is the bit used to restart the watchdog timer. Setting the RWT
bit restarts the timer for another full interval. If the watchdog timer-reset function is masked by the EWT bit and no
resets are issued to the timer through the RWT bit, the watchdog timer generates interrupt timeouts at a rate
determined by the programmed divide ratio. WDIF (WDCON.3) is the interrupt flag set at timer termination and
WTRF (WDCON.2) is the reset flag set following a watchdog reset timeout. Setting the EWDI bit (EIE.4) enables
the watchdog interrupt. The watchdog timer reset and interrupt timeouts are measured by counting system clock
cycles.
An independent watchdog timer functions as the crystal startup counter to count 65,536 crystal clock cycles before
allowing the crystal oscillator to function as the system clock. This warmup time is verified by the watchdog timer
following each power-up as well as each time the crystal is restarted following a stop mode. The watchdog is also
used to establish a startup time whenever the CTM in the PMR register is set to enable the crystal multiplier
(4X
/
2X
).
One of the watchdog timer applications is for the watchdog to wake up the system from idle mode. The watchdog
interrupt can be programmed to allow a system to wake up periodically to sample the external world.
Internal System Reset
A software reset can be initiated by writing a system reset command to the flash control SFR. The reset state is
maintained for approximately 90 external clock cycles. During this time, the RST pin is driven to a logic high. Once
the reset is removed, the RST pin is driven low, and operation begins from address 0000h.
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