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參數(shù)資料
| 型號(hào)： | DS89C430 |
| 英文描述： | Ultra-High-Speed Flash Microcontrollers |
| 中文描述： | 超高速閃存微控制器 |
| 文件頁數(shù)： | 39/48頁 |
| 文件大?。?/td> | 934K |
| 代理商： | DS89C430 |
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DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers
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during the three machine cycles following the writing of the 55h. Writing to a timed-access-protected bit outside of
these three machine cycles has no effect on the bit.
The timed-access process is address, data, and time dependent. A processor running out of control and not
executing system software statistically is not able to perform this timed sequence of steps, and as such, does not
accidentally alter the protected bits. It should be noted that this method should be used in the main body of the
system software and
never
used in an interrupt routine in conjunction with the watchdog reset. Interrupt routines
using the timed-access watchdog-reset bit (RWT) can recover a lost system and allow the resetting of the
watchdog, but the system returns to a lost condition once the RETI is executed, unless the stack is modified. Also,
it is advisable that interrupts be disabled (EA = 0) when executing the timed-access sequence, since an interrupt
during the sequence adds time, making the timed-access attempt fail.
Power Management and Clock-Divide Control
Power-management features are available that monitor the power-supply voltage levels and support low-power
operation with three power-saving modes. Such features include a bandgap voltage monitor, watchdog timer,
selectable internal ring oscillator, and programmable system clock speed. The SFRs that provide control and
application software access are the watchdog control (WDCON, D8h), extended interrupt enable (EIE, E8h),
extended interrupt flag (EXIF, 91h) and power control (PCON, 87h) registers.
System Clock-Divide Control
The programmable clock-divide control bits (CD1 and CD0) provide the processor with the ability to adapt to
different crystals and to slow the system clocks, providing lower power operation when required. An on-chip crystal
multiplier allows the DS89C430 to operate at two or four times the crystal frequency by setting the 4X/
2X
bit, and is
enabled by setting the CTM bit to a logic 1. An additional circuit provides a clock source at divide by 1024. When
used with a 7.372MHz crystal, for example, the processor executes the machine cycle in times ranging from 33.9ns
(mulitply-by-4 mode) to 138.9 s (divide-by-1024 mode) and maintains a highly accurate serial port baud rate, while
allowing the use of more cost-effective lower frequency crystals. Although the clock-divide control bits can be
written at any time, certain hardware features enhance the use of these clock controls to guarantee proper serial
port operation and to allow for a high-speed response to an external interrupt. The 01b setting of CD1 and CD0 is
reserved. It has the same effect as the setting of 10b, which forces the system clock into a divide-by-1 mode. The
DS89C430 defaults to divide-by-1 clock mode on all forms of reset.
When in divide-by-1024 mode, in order to allow a quick response to incoming data on a serial port, the system
uses the switchback mode to automatically revert to divide-by-1 mode whenever a start bit is detected. This
automatic switchback is only enabled in divide-by-1024 mode when the switchback bit (PMR.5:SWB) is set. All
other clock modes are unaffected by interrupts and serial port activity.
The oscillator multiply ratios of 4, 2, and 1 are also used to provide standard baud-rate generation for the serial
ports through a forced divide-by-12 input clock (TxMH,TxM = 00b, x = 1, 2, or 3) to the timers.
Use of the multiply-by-4 or multiply-by-2 options through the clock-divide control bits requires that the crystal
multiplier be enabled and the specific system-clock-multiply value be established by the 4X/
2X
bit in the PMR
register. The multiplier is enabled through the CTM (PMR.4) bit but cannot be automatically selected until a startup
delay has been established through the CKRY bit in the status register. The 4X/
2X
bit can only be altered when the
CTM bit is cleared to a logic 0. This prevents the system from changing the multiplier until the system has moved
back to the divide-by-1 mode and the multiplier has been disabled by the CTM bit. The CTM bit can only be altered
when the CD1 and CD0 bits are set to divide-by-1 mode and the RGMD bit is cleared to 0. Setting the CTM to a
logic 1 from a previous logic 0 automatically clears the CKRY bit in the status register and starts the multiplier
startup timeout in the multiplier startup counter. During the multiplier startup period, the CKRY bit remains cleared
and the CD1 and CD0 clock controls cannot be set to 00b. The CTM bit is cleared to a logic 0 on all resets.
Note that the rated maximum speed of operation applies to the speed of the microcontroller core, not the external
clock source. When using the clock multiplier feature, the external clock source frequency, multiplied by the clock
multiplier (2X or 4X) can never be faster than the maximum rated speed of the device. Thus, if a designer wished to
use the 4X clock multiplier on a device rated at 33MHz, the maximum external clock speed would be 8.25MHz.
Figure 14
gives a simplified description of the generation of the system clocks. Specifics of hardware restrictions
associated with the use of the 4X/
2X
CTM, CKRY, CD1, and CD0 bits are outlined in the
SFR
section.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS89C440 | Ultra-High-Speed Flash Microcontrollers |
| DS89C450 | Ultra-High-Speed Flash Microcontrollers |
| DS89C21TMX | Transceiver |
| DSDK101 | Low-Cost Demo Kit Motherboard |
| E.FL-LP-040 | CABLE ; Connector type A:MFD-Titan; Connector type B:MFD-Titan; Length, lead:5m |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS89C430_07 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:Ultra-High-Speed Flash Microcontrollers |
| DS89C430+ENG | 制造商:Maxim Integrated Products 功能描述:MCU 8BIT CISC 16KB FLASH 5V 44TQFP - Trays |
| DS89C430+ENL | 制造商:Maxim Integrated Products 功能描述:MICRO HS 44P TQFP 33MHZ IND PB-FREE - Trays |
| DS89C430+MNL | 制造商:Maxim Integrated Products 功能描述:MCU 8BIT CISC 16KB FLASH 5V 40PDIP - Rail/Tube |
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