
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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Addr
Offset
Register Name
Description
Read/Write or
Read Only
Page
2C0
Rx Real-Time Status Register 1
R
2C8
Rx Real-Time Status Register 3 (T1 Mode)
Rx Real-Time Status Register 3 (E1 Mode)
R
2D0
Rx Real-Time Status Register 5
R
2D4
Rx HDLC Packet Bytes Available Register
R
2D8
Rx HDLC FIFO Register
R
300
Rx Blank Channel Select Register 1
R/W
304
Rx Blank Channel Select Register 2
R/W
308
Rx Blank Channel Select Register 3
R/W
30C
Rx Blank Channel Select Register 4 (E1 Mode Only)
R/W
320
Rx Signaling Reinsertion Enable Reg 1
R/W
324
Rx Signaling Reinsertion Enable Reg 2
R/W
328
Rx Signaling Reinsertion Enable Reg 3
R/W
32C
Rx Signaling Reinsertion Enable Reg 4 (E1 Only)
R/W
340
Rx Channel Idle Code Enable Reg 1
R/W
344
Rx Channel Idle Code Enable Reg 2
R/W
348
Rx Channel Idle Code Enable Reg 3
R/W
34C
Rx Channel Idle Code Enable Reg 4 (E1 Only)
R/W
350
Rx BERT Port Channel Select Register 1
R/W
354
Rx BERT Port Channel Select Register 2
R/W
358
Rx BERT Port Channel Select Register 3
R/W
35C
Rx BERT Port Channel Select Register 4 (E1 Only)
R/W
Register Name:
RDMWE1-E1, RDMWE2-E1, RDMWE3-E1, RDMWE4-E1
Register Description:
Receive Digital Milliwatt Enable Registers (E1 Mode Only)
Register Address:
base address + 0x000, 0x004, 0x008, 0x00C
Bit #
7
6
5
4
3
2
1
0
RDMWE1-E1
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
RDMWE2-E1
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
RDMWE3-E1
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
RDMWE4-E1
CH32
CH31
CH30
CH29
CH28
CH27
CH26
CH25
Note: These registers are only used in E1 mode. The
RDMWE1-T1 –
RDMWE3-T1 registers are used in T1 mode.
Bits 7 to 0 (x4): E1 Rx Digital Milliwatt Enable for Channels 1 to 32 (CH1 to CH32). Register bit
RCR3.uALAW
specifies whether u-law or A-law coding is used for the digital milliwatt code. See section
10.11.13.
0 = Do not affect the Rx data associated with this channel
1 = Replace the Rx data associated with this channel with digital milliwatt code
Register Name:
RHC
Register Description:
Receive HDLC Control Register
Register Address:
base address + 0x040
Bit #
7
6
5
4
3
2
1
0
Name
RCRCD
RHR
RHMS
RHCS4
RHCS3
RHCS2
RHCS1
RHCS0
Default
0
Bit 7: Receive CRC-16 Display (RCRCD). See section
10.12.1.
0 = Do not write received CRC-16 code to FIFO. (default)
1 = Write received CRC-16 code to FIFO after last octet of packet.