參數(shù)資料
型號： DS33ZH11
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 網(wǎng)絡接口
英文描述： Ethernet Mapper
中文描述： DATACOM, NETWORK INTERFACE SUPPORT CIRCUIT, PBGA100
封裝： 10 X 10 MM, 1.41 MM HEIGHT, 0.80 MM PITCH, CSBGA-100
文件頁數(shù)： 84/169頁
文件大小： 1049K
代理商： DS33ZH11
DS33Z11 Ethernet Mapper
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 3 – 5: Transmit Error Insertion Rate (TEIR[2:0])
These three bits indicate the rate at which errors are
inserted in the output data stream. One out of every 10
bits is inverted. TEIR[2:0] is the value n. A TEIR[2:0] value
of 0 disables error insertion at a specific rate. A TEIR[2:0] value of 1 result in every 10
bit being inverted. A
TEIR[2:0] value of 2 results in every 100
bit being inverted. Error insertion starts when this register is written to
with a TEIR[2:0] value that is non-zero. If this register is written to during the middle of an error insertion process,
the new error rate is started after the next error is inserted.
84 of 169
TEICR
Transmit Error Insertion Control Register
88h
7
-
0
6
-
0
5
4
3
2
1
0
-
0
TIER2
0
TIER1
0
TIER0
0
BEI
0
TSEI
0
Bit 2: Bit Error Insertion Enable (BEI)
When 0, single bit error insertion is disabled. When 1, single bit error
insertion is enabled.
Bit 1: Transmit Single Error Insert (TSEI)
This bit causes a bit error to be inserted in the transmit data stream if
and single bit error insertion is enabled. A 0 to 1 transition causes a single bit error to be inserted. For a second bit
error to be inserted, this bit must be set to 0, and back to 1. Note: If this bit transitions more than once between
error insertion opportunities, only one error is inserted.
All other bits in this register besides BEI and TSEI and TIER must be reset to 0 for proper operation.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
BSR
BERT Status Register
8Ch
7
-
0
6
-
0
5
-
0
4
-
0
3
2
-
0
1
0
PMS
0
BEC
0
OOS
0
Bit 3: Performance Monitoring Update Status (PMS)
This bit indicates the status of the receive performance
monitoring register (counters) update. This bit will transition from low to high when the update is completed. PMS
is asynchronously forced low when the PMU bit goes low. TCLKI and RCLKI must be present.
Bit 1: Bit Error Count (BEC)
When 0, the bit error count is zero. When 1, the bit error count is one or more.
Bit 0: Out Of Synchronization (OOS)
When 0, the receive pattern generator is synchronized to the incoming
pattern. When 1, the receive pattern generator is not synchronized to the incoming pattern.
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