參數(shù)資料
型號： DS33ZH11
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 網(wǎng)絡接口
英文描述： Ethernet Mapper
中文描述： DATACOM, NETWORK INTERFACE SUPPORT CIRCUIT, PBGA100
封裝： 10 X 10 MM, 1.41 MM HEIGHT, 0.80 MM PITCH, CSBGA-100
文件頁數(shù)： 79/169頁
文件大?。?/td> 1049K
代理商： DS33ZH11
DS33Z11 Ethernet Mapper
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
79 of 169
GL.C1QPR
Connection 1 Queue Pointer Reset
12h
7
-
0
6
-
0
5
-
0
4
-
0
3
2
1
0
C1MRPRR
0
C1HWPRR
0
C1MHPR
0
C1HRPR
0
Bit 3: MAC Read Pointer Reset (C1MRPRR)
If this
bit is set to 1, the receive queue read pointer is reset for
connection 1. The queue pointer must be reset after a disconnect and before a connection.
Bit 2: HDLC Write Pointer Reset (C1HWPRR)
If this
bit is set to 1, the receive queue write pointer is reset for
connection 1. The queue pointer must be reset after a disconnect and before a connection.
Bit 1: HDLC Read Pointer Reset (C1MHPR)
If this
bit is set to 1, the receive queue read pointer is reset for
connection 1. The queue pointer must be reset after a disconnect and before a connection.
Bit 0: MAC Transmit Write Pointer Reset (C1HRPR)
If this
bit is set to 1, the receive queue write pointer is reset
for connection 1. The queue pointer must be reset after a disconnect and before a connection.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
GL.BISTEN
BIST Enable
20h
7
-
0
6
-
0
5
-
0
4
-
0
3
-
0
2
-
0
1
-
0
0
BISTE
0
Bit 0: BIST Enable (BISTE)
If this bit is set the DS33Z11 performs BIST test on the SDRAM. Normal data
communication is halted while BIST enable is high. The user must reset the DS33Z11 after completion of BIST
test before normal dataflow can begin.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
GL.BISTPF
BIST PassFail
21h
7
-
0
6
-
0
5
-
0
4
-
0
3
-
0
2
-
0
1
0
BISTDN
0
BISTPF
0
Bit 1: BIST DONE (BISTDN)
If this bit is set to 1, the DS33Z11 has completed the BIST Test initiated by BISTE.
The pass fail result is available in BISTPF.
Bit 0: BIST PassFail (BISTPF)
This bit is equal to 0 after the DS33Z11 performs BIST testing on the SDRAM and
the test passes. This bit is set to 1 if the test failed. This bit is valid only after the BIST test is complete and the
BIST DN bit is set. If set this bit can only be cleared by resetting the DS33Z11.
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