參數(shù)資料
型號: DS33ZH11
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 網(wǎng)絡(luò)接口
英文描述: Ethernet Mapper
中文描述: DATACOM, NETWORK INTERFACE SUPPORT CIRCUIT, PBGA100
封裝: 10 X 10 MM, 1.41 MM HEIGHT, 0.80 MM PITCH, CSBGA-100
文件頁數(shù): 73/169頁
文件大?。?/td> 1049K
代理商: DS33ZH11
DS33Z11 Ethernet Mapper
73 of 169
9.2 Global Register Definitions
Functions contained in the global registers include: framer reset, LIU reset, device ID, BERT interrupt status,
framer interrupt status, MCLK configuration, and BPCLK configuration. These registers are preserved to provide
code compatibility with the multiport devices in this product family. The global registers bit descriptions are
presented below.
Register Name:
GL.IDRL
Register Description:
Global ID Low Register
Register Address:
00h
Bit #
7
6
5
4
Name
ID07
ID06
ID05
ID04
Default
0
0
1
1
Bit 7: ID07
Reserved for future use
Bit 6: ID06
Reserved for future use
Bit 5: ID05
If this bit is set the device contains a RMII interface
Bit 4: ID04
If this bit is set the device contains a MII interface
Bit 3: ID03
If this bit is set the device contains an Ethernet PHY
Bits 0-2: ID00-ID02
A three-bit count that is equal to 000b for the first die revision, and is incremented with each
successive die revision. May not match the two-letter die revision code on the top brand of the device.
3
2
1
0
ID03
0
ID02
0
ID01
0
ID00
0
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 5-7: ID13-15
Number of ports in the device – 1. (i.e. 000 = 1 port)
Bit 4: ID12
If this bit is set the device has LIU functionality
Bit 3: ID11
If this bit is set the device has a framer
Bit 2: ID10
Reserved for future use
Bit 1: ID09
If this bit is set the device has HDLC or X.86 encapsulation
Bit 0: ID08
If this bit is set the device has inverse multiplexing functionality
GL.IDRH
Global ID High Register
01h
7
6
5
4
3
2
1
0
ID15
0
ID14
0
ID13
0
ID12
0
ID11
0
ID10
0
ID09
1
ID08
0
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