- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385274 > DS33Z11 (MAXIM INTEGRATED PRODUCTS INC) Ethernet Mapper PDF資料下載
參數(shù)資料
| 型號： | DS33Z11 |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | Ethernet Mapper |
| 中文描述： | DATACOM, NETWORK INTERFACE SUPPORT CIRCUIT, PBGA169 |
| 封裝： | 14 X 14 MM, 1 MM PITCH, CSBGA-169 |
| 文件頁數(shù)： | 5/169頁 |
| 文件大?。?/td> | 1049K |
| 代理商： | DS33Z11 |
第1頁第2頁第3頁第4頁當前第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁
DS33Z11 Ethernet Mapper
5 of 169
LIST OF FIGURES
Figure 3-1 Ethernet to WAN Extension (No Framing)..............................................................................................11
Figure 3-2 Ethernet to WAN Extension (T1E1 Framing and LIU) ............................................................................12
Figure 3-3 Ethernet to WAN Extension with T3/E3 Framing....................................................................................12
Figure 3-4 Ethernet over DSL...................................................................................................................................13
Figure 3-5 Copper to Fiber Connection ....................................................................................................................13
Figure 6-1 Detailed Block Diagram...........................................................................................................................16
Figure 7-1 DS33Z11 169-Ball CSBGA Pinout ..........................................................................................................27
Figure 7-2 DS33ZH11 100-Ball CSBGA Pinout (Hardware or SPI Mode Only) .......................................................28
Figure 8-1 Clocking for the DS33Z11.......................................................................................................................32
Figure 8-2 Device Interrupt Information Flow Diagram.............................................................................................37
Figure 8-3 Flow Control Using Pause Control Frame...............................................................................................42
Figure 8-4 IEEE 802.3 Ethernet Frame....................................................................................................................43
Figure 8-5 Configured as DTE Connected to an Ethernet PHY in MII Mode............................................................45
Figure 8-6 DS33Z11 Configured as a DCE in MII Mode ..........................................................................................46
Figure 8-7 RMII Interface..........................................................................................................................................48
Figure 8-8 MII Management Frame..........................................................................................................................49
Figure 8-9 PRBS Synchronization State Diagram ....................................................................................................51
Figure 8-10 Repetitive Pattern Synchronization State Diagram ...............................................................................52
Figure 8-11 LAPS Encoding of MAC Frames Concept.............................................................................................56
Figure 8-12 X.86 Encapsulation of the MAC field.....................................................................................................57
Figure 8-13 CIR in the WAN Transmit Path .............................................................................................................60
Figure 10-1 TX Serial Interface Functional Timing.................................................................................................139
Figure 10-2 RX Serial Interface Functional Timing.................................................................................................139
Figure 10-3 Transmit Byte Sync Functional timing.................................................................................................140
Figure 10-4 Receive Byte Sync Functional Timing.................................................................................................140
Figure 10-5 MII Transmit Functional Timing...........................................................................................................141
Figure 10-6 MII Transmit Half Duplex with a Collision Functional Timing ..............................................................141
Figure 10-7 MII Receive Functional Timing............................................................................................................141
Figure 10-8 RMII Transmit Interface Functional Timing.........................................................................................141
Figure 10-9 RMII Receive Interface Functional Timing ..........................................................................................142
Figure 10-10 SPI Master Functional Timing...........................................................................................................142
Figure 11-1 Transmit MII Interface .........................................................................................................................146
Figure 11-2 Receive MII Interface Timing...............................................................................................................147
Figure 11-3 Transmit RMII Interface.......................................................................................................................148
Figure 11-4 Receive RMII Interface Timing............................................................................................................149
Figure 11-5 MDIO Timing.......................................................................................................................................150
Figure 11-6 Transmit WAN Timing.........................................................................................................................151
Figure 11-7 Receive WAN timing ...........................................................................................................................152
Figure 11-8 SDRAM Interface Timing.....................................................................................................................154
Figure 11-9 Intel Bus Read Timing (HWMODE = 0, MODEC = 00).......................................................................156
Figure 11-10 Intel Bus Write Timing (HWMODE = 0, MODEC = 00).....................................................................156
Figure 11-11 Motorola Bus Read Timing (HWMODE = 0, MODEC = 01)..............................................................157
Figure 11-12 Motorola Bus Write Timing (HWMODE = 0, MODEC = 01)..............................................................157
Figure 11-13 EEPROM Interface Timing................................................................................................................158
Figure 11-14 JTAG Interface Timing Diagram........................................................................................................159
Figure 12-1 JTAG Functional Block Diagram.........................................................................................................160
Figure 12-2 TAP Controller State Diagram.............................................................................................................163
Figure 12-3 JTAG Functional Timing......................................................................................................................166
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS33ZH11 | Ethernet Mapper |
| DS3803 | 1024K Flexible NV SRAM SIMM(1024K靈活的非易失性SRAM SIMM) |
| DS3903E-020 | Triple 128-Position Nonvolatile Digital Potentiometer |
| DS3994 | 4-Channel Cold-Cathode Fluorescent Lamp Controller |
| DS4077 | 77.76MHz VCXO |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS33Z11+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Ethernet Mapper RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS33Z11+UNUSED | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Ethernet Mapper RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS33Z11DK | 功能描述:以太網(wǎng)開發(fā)工具 DS33Z11 Dev Kit RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評估:KSZ8873RLL 接口類型:RMII 工作電源電壓: |
| DS33Z41 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad IMUX Ethernet Mapper RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS33Z41DK | 功能描述:以太網(wǎng)開發(fā)工具 DS33Z41 Dev Kit RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評估:KSZ8873RLL 接口類型:RMII 工作電源電壓: |
發(fā)布緊急采購，3分鐘左右您將得到回復。