參數(shù)資料
型號： DS33Z11
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 網絡接口
英文描述： Ethernet Mapper
中文描述： DATACOM, NETWORK INTERFACE SUPPORT CIRCUIT, PBGA169
封裝： 14 X 14 MM, 1 MM PITCH, CSBGA-169
文件頁數(shù)： 17/169頁
文件大?。?/td> 1049K
代理商： DS33Z11
DS33Z11 Ethernet Mapper
17 of 169
7 PIN DESCRIPTIONS
7.1 Pin Functional Description
Note that all digital pins are IO pins in JTAG mode. This feature increases the effectiveness of board level ATPG
patterns. JTAG pins are not available on the Hardware mode/SPI-only DS33ZH11 (10mm CSBGA)
Note:
I = Input; O = Output; Ipu = Input, with pullup; Oz = Output, with tri-state; IO = Bidirectional pin; IOz = Bidirectional pin, with tri-state
Table 7-1 Detailed Pin Descriptions
NAME
PIN #
DS33Z11
CSBGA (169)
PIN #
DS33ZH11
BGA(100)
TYPE
FUNCTION
SERIAL INTERFACE IO PINS
Serial Interface Transmit Clock Input:
The clock
reference for TSER, which is output on the rising edge of
the clock. TCLKI supports gapped clocking, up to a
maximum frequency of 52 MHz.
Transmit Serial Data Output:
Output on the rising edge
of TCLKI. Selective clock periods can be skipped for
output of TSER dependent on the TDEN settings or
gapped clock input (TCLKI). The maximum data rate is 52
Mbps.
Transmit Data Enable (Input):
The transmit data enable
is programmable to selectively block/enable the transmit
data. The TDEN signal must occur one clock edge prior to
the affected data bit. The active polarity of TDEN is
programmable in register LI.TSLCR. It is recommended
for both T1/E1 and T3/E3 applications that use gapped
clocks. The TDEN signal is provided for interfacing to
framers that do not have a gapped clock facility.
Transmit Byte Sync (Output):
This output can be used
by an external Serial to Parallel to convert TSER stream to
byte wide data. This output indicates the last bit of the byte
data sent serially on TSER. This signal is only active in the
X.86 Mode.
Note that while in Hardware mode with HDLC (non X.86)
operation, this pin must be tied high.
Serial Interface Receive Clock Input:
Reference clock
for receive serial data on RSER. Gapped clocking is
supported, up to the maximum RCLKI frequency of 52
MHz.
Receive Serial Data Input:
Receive Serial data arrives on
the rising edge of the clock.
TCLKI
F1
B1
I
TSER
F2
A2
O
TDEN/
TBSYNC
F5
—
IO
RCLKI
G2
B2
I
RSER
H1
B3
I
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PDF描述
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相關代理商/技術參數(shù)
參數(shù)描述
DS33Z11+ 功能描述:網絡控制器與處理器 IC Ethernet Mapper RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS33Z11+UNUSED 功能描述:網絡控制器與處理器 IC Ethernet Mapper RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS33Z11DK 功能描述:以太網開發(fā)工具 DS33Z11 Dev Kit RoHS:否 制造商:Micrel 產品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評估:KSZ8873RLL 接口類型:RMII 工作電源電壓:
DS33Z41 功能描述:網絡控制器與處理器 IC Quad IMUX Ethernet Mapper RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS33Z41DK 功能描述:以太網開發(fā)工具 DS33Z41 Dev Kit RoHS:否 制造商:Micrel 產品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評估:KSZ8873RLL 接口類型:RMII 工作電源電壓:
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