參數(shù)資料
型號: DS32512DK
廠商: Maxim Integrated Products
文件頁數(shù): 71/130頁
文件大?。?/td> 0K
描述: KIT DEMO FOR DS32512
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
設計資源: DS32512 Gerber Files
標準包裝: 1
主要目的: 電信,線路接口單元(LIU)
已用 IC / 零件: DS32512
DS32506/DS32508/DS32512
45 of 130
continues to transmit, the DS325xx continues to write the data received and increment its address counter. After
the address counter reaches 7FFh it rolls over to address 000h and continues to increment.
Burst Reads.
See Figure 8-11. After CS goes low, the bus master transmits a read control word with BURST = 1.
The DS325xx then responds with the requested data byte on SDO, increments its address counter, and prefetches
the next data byte. If the bus master continues to demand data, the DS325xx continues to provide the data on
SDO, increment its address counter, and prefetch the following byte. After the address counter reaches 7FFh it
rolls over to address 000h and continues to increment.
Early Termination of Bus Transactions.
The bus master can terminate SPI bus transactions at any time by
pulling
CS high. In response to early terminations, the DS325xx resets its SPI interface logic and waits for the start
of the next transaction. If a write transaction is terminated prior to the SCLK edge that latches the LSB of a data
byte, the current data byte is not written.
Design Option: Wiring SDI and SDO Together.
Because communication between the bus master and the
DS325xx is half-duplex, the SDI and SDO pins can be wired together externally to reduce wire count. To support
this option, the bus master must not drive the SDI/SDO line when the DS325xx is transmitting.
AC Timing.
See Table 11-9 and Figure 11-11 for AC timing specifications for the SPI interface.
Figure 8-10. SPI Clock Polarity and Phase Options
MSB
LSB
65
43
2
1
CS
SCK
SDI/SDO
CLOCK EDGE USED FOR DATA CAPTURE (ALL MODES)
CPOL = 0, CPHA = 0
CPOL = 0, CPHA = 1
CPOL = 1, CPHA = 0
CPOL = 1, CPHA = 1
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