參數(shù)資料
型號: DS32512DK
廠商: Maxim Integrated Products
文件頁數(shù): 115/130頁
文件大?。?/td> 0K
描述: KIT DEMO FOR DS32512
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
設(shè)計資源: DS32512 Gerber Files
標(biāo)準(zhǔn)包裝: 1
主要目的: 電信,線路接口單元(LIU)
已用 IC / 零件: DS32512
DS32506/DS32508/DS32512
85 of 130
Bit 4: Receive Pattern Inversion Control (RPIC)
. See Section 8.5.1.
0 = do not invert the incoming data stream
1 = invert the incoming data stream
Bit 3: Manual Pattern Resynchronization (MPR).
A zero-to-one transition of this bit causes the receive pattern
generator to resynchronize to the incoming pattern. This bit must be changed to zero and back to one for another
resynchronization to be initiated. Note: A manual resynchronization forces the pattern detector out of the “Sync”
state. See Section 8.5.2.
Bit 2: Automatic Pattern Resynchronization Disable (APRD).
When APRD = 0, the receive pattern generator
automatically resynchronizes to the incoming pattern if six or more times during the current 64-bit window the
incoming data stream bit and the receive pattern generator output bit did not match. When APRD = 1, the receive
pattern generator does not automatically resynchronize to the incoming pattern. Note: Automatic synchronization is
prevented by not allowing the receive pattern generator to automatically exit the “Sync” state. See Section 8.5.2.
Bit 1: Transmit New Pattern Load (TNPL).
A zero-to-one transition of this bit causes the programmed test pattern
(QRSS, PTS, PLF[4:0], PTF[4:0] in the BERT.PCR register, and BSP[31:0] in the BERT.SPR registers) to be
loaded into the transmit pattern generator. This bit must be changed to zero and back to one for another pattern to
be loaded. Note: The test pattern fields mentioned above must not change for four TCLK cycles after this bit
transitions from zero to one. See Section 8.5.1.
Bit 0: Transmit Pattern Inversion Control (TPIC).
See Section 8.5.1.
0 = do not invert the outgoing data stream
1 = invert the outgoing data stream
Register Name:
BERT.PCR
Register Description:
BERT Pattern Configuration Register
Register Address:
n * 80h + 52h
Bit #
15
14
13
12
11
10
9
8
Name
PTF[4:0]
Default
0
Bit #
7
6
5
4
3
2
1
0
Name
QRSS
PTS
PLF[4:0]
Default
0
Bits 12 to 8: Pattern Tap Feedback (PTF[4:0]).
These five bits control the PRBS “tap” feedback of the pattern
generator. The “tap” feedback is from bit y of the pattern generator (y = PTF[4:0] + 1). These bits are ignored when
the BERT block is programmed for a repetitive pattern (PTS = 1). For a PRBS signal, the feedback is an XOR of bit
n and bit y. See Section 8.5.1.
Bit 6: QRSS Enable (QRSS).
See Section 8.5.1.
0 = Disabled: the pattern generator configuration is controlled by PTS, PLF[4:0], PTF[4:0], and
BSP[31:0]
1 = Enabled: the pattern generator configuration is forced to a PRBS pattern with a generating
polynomial of x
20 + x17 + 1, and the output of the pattern generator is forced to one if the next
14 output bits are all zero.
Bit 5: Pattern Type Select (PTS).
See Section 8.5.1.
0 = PRBS pattern
1 = repetitive pattern.
Bits 4 to 0: Pattern Length Feedback (PLF[4:0]).
This field controls the “l(fā)ength” feedback of the pattern
generator. The “l(fā)ength” feedback is from bit n of the pattern generator (n = PLF[4:0] + 1). For a PRBS signal, the
feedback is an XOR of bit n and bit y. For a repetitive pattern the feedback is bit n. See Section 8.5.1.
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