參數(shù)資料
型號： DS32512DK
廠商： Maxim Integrated Products
文件頁數(shù)： 61/130頁
文件大?。?/td> 0K
描述： KIT DEMO FOR DS32512
產(chǎn)品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
設計資源： DS32512 Gerber Files
標準包裝： 1
主要目的： 電信，線路接口單元（LIU）
已用 IC / 零件： DS32512
DS32506/DS32508/DS32512
36 of 130
Figure 8-7. Jitter Attenuation/Jitter Transfer
10
100
1k
10k
100k
1M
21.7 Hz (DS3)
16.7 Hz (E3)
25.2 Hz (STS -1)
1k
-30
-20
-10
E3 [TBR24 (1997)]
FREQUENCY (Hz)
JI
TT
E
R
A
TT
E
N
U
A
TI
O
N
(d
B
)
0
DS3 [GR - 499 (1995)]
CATEGORY I
DS325xx TYPICAL
RECEIVER JITTER
TRANSFER WITH
JITTER ATTENUATOR
DISABLED
>150k
DS325xx
DS3/E3/STS-1
MINIMUM
JITTER
ATTENUATION
WITH JITTER
ATTENUATOR
ENABLED
40Hz
DS3 [GR - 253 (1999)]
CATEGORY I
27Hz
STS- 1 [GR - 253 (1999)]
CATEGORY II
40k 59.6k
DS3 [GR - 499 (1999)]
CATEGORY II
8.5 BERT
Each LIU port has a built-in bit error-rate tester (BERT). The BERT is a software-programmable test-pattern
generator and monitor capable of meeting most error performance requirements for digital transmission equipment.
It can generate and synchronize to pseudo-random patterns with a generation polynomial of the form x
n + xy + 1,
(where n and y can take on values from 1 to 32 with y < n) and to repetitive patterns of any length up to 32 bits.
The pattern generator generates the programmable test pattern, and inserts the test pattern into the data stream.
The pattern detector extracts the test pattern from the receive data stream and monitors it. Figure 2-1 shows the
location of the BERT Block within the DS325xx devices.
8.5.1 Configuration and Monitoring
The pattern detector is always enabled. The pattern generator is enabled by setting the PORT.CR3:BERTE
configuration bit. When the BERT is enabled and PORT.CR3:BERTD=0, the pattern is transmitted and received in
the line direction, i.e. the pattern generator is the data source for the transmitter, and the receiver is the data source
for the pattern detector. When the BERT is enabled and PORT.CR3:BERTD=1, the pattern is transmitted and
received in the system direction, i.e. the pattern generator is the data source for the RPOS/RDAT and RNEG/RLCV
pins, and the TPOS/TDAT and TNEG pins are the data source for the pattern detector. See Figure 2-1.
The I/O of the BERT are binary (NRZ) format. Thus while the BERT is enabled, both PORT.CR2:RBIN and
PORT.CR2:TBIN must be set to 1 for proper operation. In addition, while transmitting/receiving BERT patterns in
the system direction (PORT.CR3:BERTD = 1), the neighboring framer or mapper component must also be
configured for binary interface mode to match the LIU. If the LIU interface is normally bipolar, the interface can be
changed back to bipolar mode when the system is done using the BERT function (PORT.CR3:BERTE = 0).
The following tables show how to configure the BERT to send and receive common patterns.
相關PDF資料
PDF描述
DS3253DK KIT DEMO FOR DS3253
DS26522DK KIT DESIGN FOR DS26522
EMM08DSEF-S13 CONN EDGECARD 16POS .156 EXTEND
DS26528DK KIT DESIGN FOR DS26528
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相關代理商/技術參數(shù)
參數(shù)描述
DS32512N 功能描述:網(wǎng)絡控制器與處理器 IC 12-Port DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS32512N# 功能描述:網(wǎng)絡控制器與處理器 IC 12-Port DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS32512N+ 功能描述:網(wǎng)絡控制器與處理器 IC 12-Port DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS32512NA2 制造商:Maxim Integrated Products 功能描述:DS32512 X12 DS3/E3 LIU REVA2 IND - Rail/Tube
DS32512NW 功能描述:網(wǎng)絡控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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