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| 型號(hào)： | DS32512+ |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 48/130頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU DS3/E3/STS-1 484-BGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 30 |
| 類型： | 線路接口裝置（LIU） |
| 規(guī)程： | DS3 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 484-BGA |
| 供應(yīng)商設(shè)備封裝： | 484-BGA（23x23） |
| 包裝： | 管件 |
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8. FUNCTIONAL DESCRIPTION
8.1 LIU Mode
Each port is independently configurable for DS3, E3 or STS-1 operation. When only the hardware interface is
enabled (IFSEL = 000 and HW = 1), the LMn[1:0] pins specify the LIU mode. When a microprocessor interface is
enabled (IFSEL
≠ 000) the PORT.CR2:LM[1:0] control bits specify the LIU mode.
8.2 Transmitter
8.2.1 Transmit Clock
If the jitter attenuator is not enabled in the transmit path, the signal on TCLK is the transmit line clock and must be
transmission quality (i.e.,
±20ppm frequency accuracy and low jitter). If the jitter attenuator is enabled in the
transmit path, the signal on TCLK can be jittery and/or periodically gapped, but must still have an average
frequency within
±20ppm of the nominal line rate. When enabled in the transmit path, the jitter attenuator generates
the transmit line clock. See Section 8.4 for more information about the jitter attenuator.
The polarity of TCLK can be inverted to support glueless interfacing to a variety of neighboring components.
Normally data is sampled on the TPOS/TDAT and TNEG pins on the rising edge of TCLK. To sample these pins on
8.2.1.1
Transmit Common Clock Mode
When the TCC pin is high, the transmit paths of all ports are clocked from TCLK1 and pins TCLKx (x
≠ 1) are
ignored. When the TCC pin is low, the PORT.CR2:TCC register bit specifies whether the transmit clock for port n
comes from TCLKn or TCLK1. In designs where the transmit paths of all ports can be clocked synchronously with
one another, common transmit clocking reduces wiring complexity between the LIU and the neighboring framer or
mapper component.
8.2.2 Framer Interface Format and the B3ZS/HDB3 Encoder
Data to be transmitted can be input in either bipolar or binary format.
8.2.2.1
Bipolar Interface Format
To select the bipolar interface format, pull the TBIN pin low and clear the PORT.CR2:TBIN configuration bit. In
bipolar format, the B3ZS/HDB3 encoder is disabled and the data to be transmitted is sampled on the TPOS and
TNEG pins. Positive-polarity pulses are indicated by TPOS = 1, while negative-polarity pulses are indicated by
TNEG = 1. If TPOS and TNEG are high at the same time the transmitter generates an AMI pulse that is the
opposite state of the pulse previously transmitted.
8.2.2.2
Binary Interface Format
To select the binary interface format, pull the TBIN pin high (all ports) or set the PORT.CR2:TBIN configuration bit
(per port). In binary format, the B3ZS/HBD3 encoder is enabled, and the NRZ data to be transmitted is sampled on
the TDAT pin. The TNEG pin is ignored in binary interface mode and should be wired low. In DS3 and STS-1
modes, B3ZS encoding is performed. In these modes, whenever three consecutive zeros are found in the transmit
data stream they are replaced with a B3ZS codeword. In E3 mode HDB3 encoding is performed. In this mode,
whenever four consecutive zeros are found in the transmit data stream they are replaced with an HDB3 codeword.
In all three modes, the B3ZS or HDB3 codeword is constructed such that the last bit is a BPV with the opposite
polarity of the most recently transmitted BPV.
8.2.3 Error Insertion
Bipolar violation (BPV) errors and excessive zeros (EXZ) errors can be inserted into the transmit data stream using
the transmit manual error insert (TMEI) logic (see Section 8.7.5). Configuration bit LINE.TCR:BPVI enables the
insertion of bipolar violations, while LINE.TCR:EXZI enables the insertion of excessive zero events. Note: BPV
errors and EXZ errors can only be inserted in the binary interface format.
If the transmitter is configured for binary interface format (Section 8.2.2.2) and BPVI = 1 then when the configured
manual error insert control goes from zero to one, the transmitter waits for the next occurrence of two consecutive
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS32512+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 12-Port DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS32512A2 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 12-Port DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS32512DK | 功能描述:網(wǎng)絡(luò)開發(fā)工具 DS32512 Dev Kit RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評(píng)估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V |
| DS32512N | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 12-Port DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS32512N# | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 12-Port DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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