參數(shù)資料
型號: DS32512+
廠商: Maxim Integrated Products
文件頁數(shù): 110/130頁
文件大?。?/td> 0K
描述: IC LIU DS3/E3/STS-1 484-BGA
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 30
類型: 線路接口裝置(LIU)
規(guī)程: DS3
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 484-BGA
供應(yīng)商設(shè)備封裝: 484-BGA(23x23)
包裝: 管件
DS32506/DS32508/DS32512
80 of 130
9.7 B3ZS/HDB3 Decoder Registers
ADDRESS
OFFSET
REGISTER
REGISTER DESCRIPTION
40h
B3ZS/HDB3 Receive Control Register
42h
Unused
44h
B3ZS/HDB3 Receive Status Register
46h
B3ZS/HDB3 Receive Status Register Latched
48h
B3ZS/HDB3 Receive Status Register Interrupt Enable
4Ah
Unused
4Ch
B3ZS/HDB3 Receive Bipolar Violation Count Register
4Eh
B3ZS/HDB3 Receive Excessive Zero Count Register
Register Name:
LINE.RCR
Register Description:
B3ZS/HDB3 Receive Control Register
Register Address:
n * 80h + 40h
Bit #
15
14
13
12
11
10
9
8
Name
Default
0
Bit #
7
6
5
4
3
2
1
0
Name
E3CVE
REZSF
RDZSF
RZSD
Default
0
Bit 3: E3 Code Violation Enable (E3CVE).
In E3 mode (PORT.CR2:LM[1:0] = 01), this bit specifies whether the
LINE.RBPVCR register counts bipolar violations or E3 coding violations. Note: E3 line coding violations are defined
in ITU O.161 as consecutive bipolar violations of the same polarity. This bit is ignored in B3ZS mode. See Section
0 = bipolar violations.
1 = E3 line coding violations
Bit 2: Receive BPV Error Detection Zero Suppression Code Format (REZSF).
When REZSF = 0, BPV error
detection detects a B3ZS signature if a zero is followed by a bipolar violation (BPV), and an HDB3 signature if two
zeros are followed by a BPV. When REZSF = 1, BPV error detection detects a B3ZS signature if a zero is followed
by a BPV that has the opposite polarity of the BPV in the previous B3ZS signature, and an HDB3 signature if two
zeros are followed by a BPV that has the opposite polarity of the BPV in the previous HDB3 signature. Note:
Immediately after a reset (RST or DPRST bit high), this bit is ignored. The first B3ZS signature is defined as a zero
followed by a BPV, and the first HDB3 signature is defined as two zeros followed by a BPV. All subsequent
B3ZS/HDB3 signatures are determined by the setting of this bit. Note: The default setting (REZSF = 0) conforms to
ITU O.162. The default setting may falsely ignore actual BPVs that are not codewords. It is recommended that
REZSF be set to one for most applications. This setting is more robust to accurately detect codewords.
See
Section 8.3.6.2.
Bit 1: Receive Zero Suppression Decoding Zero Suppression Code Format (RDZSF).
When RDZSF = 0, zero
suppression decoding detects a B3ZS signature if a zero is followed by a bipolar violation (BPV), and an HDB3
signature if two zeros are followed by a BPV. When RDZSF = 1, zero suppression decoding detects a B3ZS
signature if a zero is followed by a BPV that has the opposite polarity of the BPV in the previous B3ZS signature,
and an HDB3 signature if two zeros are followed by a BPV that has the opposite polarity of the BPV in the previous
HDB3 signature. Note: Immediately after a reset (RST or DPRST bit high), this bit is ignored. The first B3ZS
signature is defined as a zero followed by a BPV, and the first HDB3 signature is defined as two zeros followed by
a BPV. All subsequent B3ZS/HDB3 signatures are determined by the setting of this bit. Note: The default setting
(RDZSF = 0) may falsely decode actual BPVs that are not codewords. It is recommended that RDZSF be set to
one for most applications. This setting is more robust to accurately detect codewords.
See Section 8.3.6.2.
Bit 0: Receive Zero Suppression Decoding Disable (RZSD)
0 = zero suppression (B3ZS or HDB3) decoding is enabled
1 = zero suppression (B3ZS or HDB3) decoding is disabled, and only AMI decoding is performed
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