±5ppm, I2C Real-Time Clock with SRAM 12 Maxim Integrated Real-Time Clock" />
參數(shù)資料
型號: DS3232MZ+
廠商: Maxim Integrated Products
文件頁數(shù): 4/23頁
文件大?。?/td> 0K
描述: IC RTC W/SRAM I2C 8SOIC
標準包裝: 100
類型: 時鐘/日歷
特點: 警報器,閏年,方波輸出,SRAM
存儲容量: 236B
時間格式: HH:MM:SS(12/24 小時)
數(shù)據(jù)格式: YY-MM-DD-dd
接口: I²C,2 線串口
電源電壓: 2.3 V ~ 4.5 V
電壓 - 電源,電池: 2.3 V ~ 4.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應商設備封裝: 8-SOIC
包裝: 管件
DS3232M
±5ppm, I2C Real-Time Clock with SRAM
12
Maxim Integrated
Real-Time Clock (RTC)
With the 1Hz source from the temperature-compensated
oscillator, the RTC provides seconds, minutes, hours,
day, date, month, and year information. The date at the
end of the month is automatically adjusted for months
with fewer than 31 days, including corrections for leap
year. The clock operates in either the 24-hour or the
12-hour format with an AM/PM indicator. The clock pro-
vides two programmable time-of-day alarms. INT/SQW
can be enabled to generate either an interrupt due to an
alarm condition or a 1Hz square wave. This selection is
controlled by the INTCN bit in the Control register.
I2C Interface
The I2C interface is accessible whenever either VCC or
VBAT is at a valid level. If a microcontroller connected
to the device resets because of a loss of VCC or other
event, it is possible that the microcontroller and device’s
I2C communications could become unsynchronized,
e.g., the microcontroller resets while reading data from
the device. When the microcontroller resets, the device’s
I2C interface can be placed into a known state by tog-
gling SCL until SDA is observed to be at a high level. At
that point the microcontroller should pull SDA low while
SCL is high, generating a START condition.
SRAM
The DS3232M provides 236 bytes of general-purpose
battery-backed read/write memory. The I2C address
ranges from 14h–FFh. The SRAM can be written or read
whenever VCC or VBAT is greater than the minimum oper-
ating voltage.
Address Map
Table 2 shows the address map for the device’s time-
keeping registers. During a multibyte access, when
the address pointer reaches the end of the register
space (12h), it wraps around to location 00h. On an
I2C START or address pointer incrementing to location
00h, the current time is transferred to a second set of
registers. The time information is read from these sec-
ondary registers, while the clock can continue to run.
This eliminates the need to reread the registers in case
the main registers update during a read.
Clock and Calendar
The time and calendar information is obtained by reading
the appropriate register bytes. Table 2 shows the RTC
registers. The time and calendar data are set or initialized
by writing the appropriate register bytes. The contents of
the time and calendar registers are in the binary-coded
decimal (BCD) format. The device can be run in either
12-hour or 24-hour mode. Bit 6 of the Hours register is
defined as the 12-hour or 24-hour mode select bit. When
high, the 12-hour mode is selected. In the 12-hour mode,
bit 5 is the AM/PM bit with logic-high being PM. In the
24-hour mode, bit 5 is the 20-hour bit (20–23 hours).
The century bit (bit 7 of the Month register) is toggled
when the Years register overflows from 99 to 00. The
day-of-week register increments at midnight. Values that
correspond to the day of week are user-defined but must
be sequential (i.e., if 1 equals Sunday, then 2 equals
Monday, and so on). Illogical time and date entries result
in undefined operation. When reading or writing the time
and date registers, secondary buffers are used to prevent
errors when the internal registers update. When reading
the time and date registers, the secondary buffers are
synchronized to the internal registers on any I2C START
and when the register pointer rolls over to zero. The time
information is read from these secondary registers, while
the clock continues to run. This eliminates the need to
reread the registers in case the main registers update
during a read. The countdown chain is reset whenever
the seconds register is written. Write transfers occur on
the acknowledge from the device. Once the countdown
chain is reset, to avoid rollover issues the remaining time
and date registers must be written within 1s.
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