±5ppm, I2C Real-Time Clock with SRAM 19 Maxim Integrated Test Register (" />
參數(shù)資料
型號: DS3232MZ+
廠商: Maxim Integrated Products
文件頁數(shù): 11/23頁
文件大?。?/td> 0K
描述: IC RTC W/SRAM I2C 8SOIC
標(biāo)準(zhǔn)包裝: 100
類型: 時(shí)鐘/日歷
特點(diǎn): 警報(bào)器,閏年,方波輸出,SRAM
存儲(chǔ)容量: 236B
時(shí)間格式: HH:MM:SS(12/24 小時(shí))
數(shù)據(jù)格式: YY-MM-DD-dd
接口: I²C,2 線串口
電源電壓: 2.3 V ~ 4.5 V
電壓 - 電源,電池: 2.3 V ~ 4.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOIC
包裝: 管件
DS3232M
±5ppm, I2C Real-Time Clock with SRAM
19
Maxim Integrated
Test Register (13h)
SRAM (14h–FFh)
Figure 8. Software Reset I/O Execution
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
NAME:
SWRST
0
POR*:
0
*POR is defined as the first application of power to the device, either VBAT or VCC.
This register is used for factory test. Bits 6:0 are locked and always read as zeros. Writing to bit locations 6:0 has no affect on the
device. If the SWRST bit is set to Logic 1, the device immediately resets all internal logic and registers (except the SRAM) to their
factory-default POR state.
The device reset occurs during the normal acknowledge time slot following the receipt of the data byte carrying that SWRST
instruction; a NACK occurs due to the resetting action (see Figure 8). The I/O master should terminate the I/O string with a nor-
mal STOP instruction (on the 28th SCL clock). The SWRST bit is automatically cleared to logic 0.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
NAME:
D7
D6
D5
D4
D3
D2
D1
D0
POR*:
X
*POR is defined as the first application of power to the device, either VBAT or VCC.
SDA
11
0
000
00
0000
00
0
1
SCL
SLAVE ADDRESS
REGISTER ADDRESS
SLAVE ACKs
NACK DURING SWRST
DATA
R/W
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