±5ppm, I2C Real-Time Clock with SRAM 4 Maxim Integrated
參數(shù)資料
型號(hào)： DS3232MZ+
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 18/23頁(yè)
文件大?。?/td> 0K
描述： IC RTC W/SRAM I2C 8SOIC
標(biāo)準(zhǔn)包裝： 100
類型： 時(shí)鐘/日歷
特點(diǎn)： 警報(bào)器，閏年，方波輸出，SRAM
存儲(chǔ)容量： 236B
時(shí)間格式： HH:MM:SS（12/24 小時(shí)）
數(shù)據(jù)格式： YY-MM-DD-dd
接口： I²C，2 線串口
電源電壓： 2.3 V ~ 4.5 V
電壓 - 電源，電池： 2.3 V ~ 4.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 8-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 8-SOIC
包裝： 管件
DS3232M
±5ppm, I2C Real-Time Clock with SRAM
4
Maxim Integrated
Note 2: Limits are 100% tested at TA = +25°C and TA = +85°C. Limits over the operating temperature range and relevant supply
voltage range are guaranteed by design and characterization. Typical values are not guaranteed.
Note 3: Includes the temperature conversion current (averaged).
Note 4: Does not include RST leakage if VCC < VPF.
Note 5: The parameter tOSF is the period of time the oscillator must be stopped for the OSF flag to be set.
Note 6: The state of RST does not affect the I2C interface or RTC functions.
Note 7: Interface timing shown is for fast-mode (400kHz) operation. This device is also backward-compatible with standard mode
I2C timing.
Note 8: CB = total capacitance of one bus line in picofarads.
Note 9: Guaranteed by design and not 100% production tested.
AC ELECTRICAL CHARACTERISTICS—POWER SWITCH
(TA = -40NC to +85NC, unless otherwise noted.) (Note 2, Figure 2)
AC ELECTRICAL CHARACTERISTICS—I2C INTERFACE
(VCC or VBAT = +2.3V to +4.5V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = +3.3V, VBAT = +3.0V, and
TA = +25NC, unless otherwise noted.) (Notes 2, 7, Figure 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VCC Fall Time, VPFMAX to
VPFMIN
tVCCF
300
F
s
VCC Rise Time, VPFMIN to
VPFMAX
tVCCR
0
F
s
Recovery at Power-Up
tREC
(Note 6)
250
300
ms
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCL Clock Frequency
fSCL
0
400
kHz
Bus Free Time Between STOP
and START Conditions
tBUF
1.3
F
s
Hold Time (Repeated) START
Condition
tHD:STA
0.6
F
s
Low Period of SCL
tLOW
1.3
F
s
High Period of SCL
tHIGH
0.6
F
s
Data Hold Time
tHD:DAT
0
0.9
F
s
Data Set-Up Time
tSU:DAT
100
ns
START Set-Up Time
tSU:STA
0.6
F
s
SDA and SCL Rise Time
tR
(Note 8)
20 +
0.1CB
300
ns
SDA and SCL Fall Time
tF
(Note 8)
20 +
0.1CB
300
ns
STOP Set-Up Time
tSU:STO
0.6
F
s
SDA, SCL Input Capacitance
CBIN
(Note 9)
10
pF
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