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參數(shù)資料
| 型號(hào)： | DS3134 |
| 英文描述： | Chateau Channelized T1 And E1 And HDLC Controller |
| 中文描述： | 不推薦用于新設(shè)計(jì) |
| 文件頁(yè)數(shù)： | 109/203頁(yè) |
| 文件大?。?/td> | 777K |
| 代理商： | DS3134 |
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DS3134
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Status / Interrupts
On each read of the Free Queue by the DMA, the DMA will set either the Status Bit for Receive DMA
Large Buffer Read (RLBR) or the Status Bit for Receive DMA Small Buffer Read (RSBR) in the Status
Register for DMA (SDMA). The DMA also checks the Receive Free Queue Large Buffer Host Write
Pointer and the Receive Free Queue Small Buffer Host Write Pointer to make sure that an underflow does
not occur. If it does occur, then the DMA will set either the Status Bit for Receive DMA Large Buffer
Read Error (RLBRE) or the Status Bit for Receive DMA Small Buffer Read Error (RSBRE) in the Status
Register for DMA (SDMA) and it will not read the Free Queue nor will it increment the Read Pointer. In
such a scenario, the Receive FIFO may overflow if the Host does not provide Free Queue Descriptors.
Each of the status bits can also (if enabled) cause a hardware interrupt to occur. See Section 4 for more
details.
Free Queue Burst Reading
The DMA has the ability to read the Free Queue in bursts. This allows for a more efficient use of the PCI
Bus. The DMA can grab messages from the Free Queue in a group rather than one at a time, freeing up
the PCI Bus for more time critical functions.
Internal to the device there is a FIFO that can store up to 16 Free Queue Descriptors (32 dwords since
each descriptor occupies two dwords). The Free Queue can either operate in dual or singular circular
queue mode. The Free Queue can be divided into Large Buffer and Small Buffer. The LBSA (Large
Buffer Starting Address) and the LBEA (Large Buffer Ending Address) forms the Large Buffer Queue
and the SBSA (Small Buffer Starting Address) and the RFQEA (Receive Free Queue End Address) forms
the Small Buffer Queue. When the SBSA is not equal to, and greater than, the RFQEA the Free Queue is
set up in a dual circular mode. If the SBSA is equal to the RFQEA, the Free Queue is operating in a single
queue mode. When the Free Queue is operated as a dual circular queue supporting both large and small
buffers, then the FIFO is cut into two 8 message FIFOs. If the Free Queue is operated as a single circular
queue supporting only the large buffers, then the FIFO is set up as a single 16 descriptor FIFO. The Host
must configure the Free Queue FIFO for proper operation via the Receive DMA Queues Control
(RDMAQ) register (see below).
When enabled via the Receive Free Queue FIFO Enable (RFQFE) bit, the Free Queue FIFO will not read
the Free Queue until it reaches the Low Water Mark. When the FIFO reaches the Low Water Mark
(which is two descriptors in the dual mode or four descriptors in the single mode,) it will attempt to fill
the FIFO with additional descriptors by burst reading the Free Queue. Before it reads the Free Queue, it
checks (by examining the Receive Free Queue Host Write Pointer) to make sure that the Free Queue
contains enough descriptors to fill the Free Queue FIFO. If the Free Queue does not have enough
descriptors to fill the FIFO, then it will only read enough to keep from underflowing the Free Queue. If
the FIFO detects that there are no Free Queue descriptors available for it to read, then it will set the either
the Status Bit for Receive DMA Large Buffer Read Error (RLBRE) or the Status Bit for Receive DMA
Small Buffer Read Error (RSBRE) in the Status Register for DMA (SDMA) and it will not read the Free
Queue nor will it increment the Read Pointer. In such a scenario, the Receive FIFO may overflow if the
Host does not provide Free Queue Descriptors. If the Free Queue FIFO can read descriptors from the
Free Queue, then it will burst read them, increment the read pointer, and set either the Status Bit for
Receive DMA Large Buffer Read (RLBR) or the Status Bit for Receive DMA Small Buffer Read (RSBR)
in the Status Register for DMA (SDMA). See Section 4 for more details on Status Bits.
相關(guān)PDF資料 |
PDF描述 |
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| DS3160 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| DS3171 | Single/Dual/Triple/Quad DS3/E3 Single-Chip Transceivers |
| DS3171N | Single/Dual/Triple/Quad DS3/E3 Single-Chip Transceivers |
| DS3172 | Single/Dual/Triple/Quad DS3/E3 Single-Chip Transceivers |
| DS3172N | Single/Dual/Triple/Quad DS3/E3 Single-Chip Transceivers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS-313PIN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog Miscellaneous |
| DS-313-PIN | 功能描述:信號(hào)調(diào)節(jié) RoHS:否 制造商:EPCOS 產(chǎn)品:Duplexers 頻率:782 MHz, 751 MHz 頻率范圍: 電壓額定值: 帶寬: 阻抗:50 Ohms 端接類型:SMD/SMT 封裝 / 箱體:2.5 mm x 2 mm 工作溫度范圍:- 30 C to + 85 C 封裝:Reel |
| DS31400 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:8-Input, 14-Output, Dual DPLL Timing IC with Sub-ps Output Jitter |
| DS31400DK | 功能描述:時(shí)鐘和定時(shí)器開發(fā)工具 DS31400 Dev Kit RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評(píng)估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| DS31400GN | 功能描述:計(jì)時(shí)器和支持產(chǎn)品 Not Available From Mouser RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時(shí)器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
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