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參數(shù)資料
| 型號(hào)： | DS31256+ |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 6/183頁(yè) |
| 文件大小： | 0K |
| 描述： | IC CTRLR HDLC 256-CHANNEL 256BGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 控制器類型： | HDLC 控制器 |
| 接口： | 串行 |
| 電源電壓： | 3 V ~ 3.6 V |
| 電流 - 電源： | 500mA |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-BBGA |
| 供應(yīng)商設(shè)備封裝： | 256-BGA（27x27） |
| 包裝： | 管件 |
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DS31256 256-Channel, High-Throughput HDLC Controller
103 of 183
- FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD -
dword 0; Bits 0 to 31/Current Data Buffer Address. The current 32-bit address of the data buffer that is being
used. This address is used by the DMA to track where data should be written to as it comes in from the receive
FIFO.
- FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD -
dword 1; Bits 0 to 15/Current Descriptor Pointer. This 16-bit value is the offset from the receive descriptor
base address of the current receive descriptor being used by the DMA to describe the specifics of the data stored in
the associated data buffer.
- FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD -
dword 1; Bits 16 to 31/Starting Descriptor Pointer. This 16-bit value is the offset from the receive descriptor
base address of the first receive descriptor in a link-list chain of descriptors. This pointer is written into the done
queue by the DMA after a specified number of data buffers (see the threshold value below) have been filled.
- HOST MUST CONFIGURE -
dword 2; Bit 0/Channel Enable (CHEN). This bit is controlled by the host to enable and disable an HDLC
channel.
0 = HDLC channel disabled
1 = HDLC channel enabled
- HOST MUST CONFIGURE -
dword 2; Bits 1, 2/Buffer Size Select. These bits are controlled by the host to select the manner in which the
receive DMA stores incoming packet data.
00 = use large size data buffers only
01 = use small size data buffers only
10 = fill a small buffer first, followed then by large buffers as needed
11 = illegal state and should not be selected
- FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD -
dword 2; Bits 3 to 6/DMA Reserved. These could be any value when read. They should be set to 0 when the host
writes to it.
- HOST MUST CONFIGURE -
dword 2; Bits 7 to 9/Threshold. These bits are controlled by the host to determine when the DMA should write
into the done queue that data is available for processing. They cannot be set to 000 when in transparent mode
(RTRANS = 1).
000 = DMA should write to the done queue only after packet reception is complete
001 = DMA should write to the done queue after 1 data buffer has been filled
010 = DMA should write to the done queue after 2 data buffers have been filled
011 = DMA should write to the done queue after 3 data buffers have been filled
100 = DMA should write to the done queue after 4 data buffers have been filled
101 = DMA should write to the done queue after 5 data buffers have been filled
110 = DMA should write to the done queue after 6 data buffers have been filled
111 = DMA should write to the done queue after 7 data buffers have been filled
- FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD -
dword 2; Bits 10 to 14/DMA Reserved. These could be any value when read. They should be set to 0 when the
host writes to it.
- FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD -
dword 2; Bit 15/First Buffer Fill (FBF). This bit is set to 1 by the receive DMA when it is in the process of
filling the first buffer of a packet. The DMA uses this bit to determine when to switch to large buffers when the
buffer size-select field is set to 10.
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| DS3141+ | IC FRAMER DS3/E3 SNGL 144CSBGA |
| DS31412N | IC 12CH DS3/3 FRAMER 349-BGA |
| DS3150TN | IC LIU T3/E3/STS-1 IND 48-TQFP |
| DS3154N+ | IC LIU DS3/E3/STS-1 QD 144CSBGA |
| DS3164+ | IC ATM/PACKET PHY QUAD 400-BGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS31256+ | 功能描述:輸入/輸出控制器接口集成電路 256Ch High Thruput HDLC Cntlr RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| DS31256B | 功能描述:輸入/輸出控制器接口集成電路 256Ch High Thruput HDLC Cntlr RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| DS31256DK | 功能描述:網(wǎng)絡(luò)開發(fā)工具 RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評(píng)估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V |
| DS31256-W+ | 制造商:Maxim Integrated Products 功能描述:ENVOY 256 CHANNEL HDLC - WAIVER - Rail/Tube |
| DS312BNC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Industrial Control IC |
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