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| 型號(hào)： | DS31256+ |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 151/183頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CTRLR HDLC 256-CHANNEL 256BGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 控制器類(lèi)型： | HDLC 控制器 |
| 接口： | 串行 |
| 電源電壓： | 3 V ~ 3.6 V |
| 電流 - 電源： | 500mA |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 256-BBGA |
| 供應(yīng)商設(shè)備封裝： | 256-BGA（27x27） |
| 包裝： | 管件 |
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DS31256 256-Channel, High-Throughput HDLC Controller
7 of 183
Table 1-A. Data Sheet Definitions
The following terms are used throughout this data sheet.
Note: The DS31256’s ports are numbered 0 to 255; the HDLC channels are numbered 1 to 256. HDLC Channel 1 is always associated with
Port 0, HDLC Channel 2 with Port 1, and so on.
TERM
DEFINITION
BERT
Bit Error-Rate Tester
Descriptor
A message passed back and forth between the DMA and the host
Dword
Double word; a 32-bit data entity
DMA
Direct Memory Access
FIFO
First In, First Out. A temporary memory storage scheme.
HDLC
High-Level Data-Link Control
Host
The main controller that resides on the PCI Bus.
n/a
Not assigned
V.54
A pseudorandom pattern that controls loopbacks (see ANSI T1.403)
2. DETAILED DESCRIPTION
This data sheet is broken into sections detailing each of the DS31256’s blocks. See Figure 2-1 for a block
diagram.
The Layer 1 block handles the physical input and output of serial data to and from the DS31256. The
DS31256 can handle up to 60 T1 or 64 E1 data streams or two T3 data streams simultaneously. Each of
the 16 physical ports can handle up to two or four T1 or E1 data streams. Section 17 details a few
common applications for the DS31256. The Layer 1 block prepares the incoming data for the HDLC
block and grooms data from the HDLC block for transmission. The block can perform both channelized
and unchannelized loopbacks as well as search for V.54 loop patterns. It is in the Layer 1 block that the
host enables HDLC channels and assigns them to a particular port and/or DS0 channel(s). The host
assigns HDLC channels through the R[n]CFG[j] and T[n]CFG[j] registers, which are described in
Section 6.3. The Layer 1 block interfaces directly to the BERT block. The BERT block can generate and
detect both pseudorandom and repeating bit patterns, and is used to test and stress data communication
links.
The HDLC block consists of two types of HDLC controllers. There are 16 slow HDLC engines (one for
each port) that are capable of operating at speeds up to 8.192Mbps in channelized mode and up to
10Mbps in unchannelized mode. There are also three fast HDLC engines, which only reside on Ports 0,
1, and 2 and they are capable of operating at speeds up to 52Mbps. Via the RP[n]CR and TP[n]CR
registers in the Layer 1 block, the host configures Ports 0, 1, and 2 to use either the slow or the fast
HDLC engine. The HDLC engines perform all of the Layer 2 processing, including zero stuffing and
destuffing, flag generation and detection, CRC generation and checking, abort generation and checking.
In the receive path, the following process occurs. The HDLC engines collect the incoming data into
32-bit dwords and then signal the FIFO that the engine has data to transfer to the FIFO. The 16 ports are
priority decoded (Port 0 gets the highest priority) for the transfer of data from the HDLC Engines to the
FIFO Block. Please note that in a channelized application, a single port may contain up to 128 HDLC
channels and since HDLC channel numbers can be assigned randomly, the HDLC channel number has
no bearing on the priority of this data transfer. This situation is of no real concern however since the
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| DS31412N | IC 12CH DS3/3 FRAMER 349-BGA |
| DS3150TN | IC LIU T3/E3/STS-1 IND 48-TQFP |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS31256+ | 功能描述:輸入/輸出控制器接口集成電路 256Ch High Thruput HDLC Cntlr RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| DS31256B | 功能描述:輸入/輸出控制器接口集成電路 256Ch High Thruput HDLC Cntlr RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| DS31256DK | 功能描述:網(wǎng)絡(luò)開(kāi)發(fā)工具 RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類(lèi)型:Ethernet to Wi-Fi Bridges 工具用于評(píng)估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類(lèi)型:802.11 b/g, Ethernet 工作電源電壓:3.3 V |
| DS31256-W+ | 制造商:Maxim Integrated Products 功能描述:ENVOY 256 CHANNEL HDLC - WAIVER - Rail/Tube |
| DS312BNC | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Industrial Control IC |
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