參數(shù)資料
型號： DS3112DK
廠商： Maxim Integrated Products
文件頁數(shù)： 92/133頁
文件大?。?/td> 0K
描述： KIT DEMO FOR DS3112
產(chǎn)品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 1
主要目的： 接口，交叉點開關(guān)/多路復用器
已用 IC / 零件： DS3112
已供物品： 板，CD
DS3112
61 of 133
Register Name:
CPCR
Register Description:
T3 C-Bit Parity Bit Error Count Register
Register Address:
28h
Bit #
7
6
5
4
3
2
1
0
Name
CPE7
CPE6
CPE5
CPE4
CPE3
CPE2
CPE1
CPE0
Default
—
Bit #
15
14
13
12
11
10
9
8
Name
CPE15
CPE14
CPE13
CPE12
CPE11
CPE10
CPE9
CPE8
Default
—
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 15: 16-Bit T3 C-Bit Parity Bit Error Counter (CPE0 to CPE15). These bits report the number of T3
C-bit parity bit errors. When the device is not in the C-bit parity mode or when the device is in the E3 mode, this
counter is meaningless and should be ignored. A C-bit parity bit error is defined as an occurrence when the
majority decoded three CP parity bits do not match the parity calculation made on the information bits. Via the
ECC control bit in the T3/E3 control register (Section 5.2), the CPCR can be configured to either continue counting
C-bit parity bit errors during a LOF or not.
Register Name:
FEBECR
Register Description:
T3 Far End Block Error or E3 RAI Count Register
Register Address:
2Ah
Bit #
7
6
5
4
3
2
1
0
Name
FEBE7
FEBE6
FEBE5
FEBE4
FEBE3
FEBE2
FEBE1
FEBE0
Default
—
Bit #
15
14
13
12
11
10
9
8
Name
FEBE15
FEBE14
FEBE13
FEBE12
FEBE11
FEBE10
FEBE9
FEBE8
Default
—
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 15: 16-Bit T3 Far End Block Error or E3 RAI Counter (FEBE0 to FEBE15). In the T3 C-bit parity
mode, these bits report the number of T3 Far End Block Errors (FEBE). This counter increments each time the
three FEBE bits do not equal 111. In the E3 Mode, these bits report the number of times the RAI bit is received in
the “disturbed state” (i.e., the number of times that it is set to a one). In the T3 mode, when the device is not in the
C-bit parity mode, this counter is meaningless and should be ignored. Via the ECC control bit in the T3/E3 control
register (Section 5.2), the FEBECR can be configured to either continue counting FEBEs or active RAI bits during
a LOF or not.
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