參數(shù)資料
型號(hào)： DS3112DK
廠商： Maxim Integrated Products
文件頁數(shù)： 66/133頁
文件大?。?/td> 0K
描述： KIT DEMO FOR DS3112
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，交叉點(diǎn)開關(guān)/多路復(fù)用器
已用 IC / 零件： DS3112
已供物品： 板，CD
DS3112
38 of 133
4.3 Master Status and Interrupt Register Description
4.3.1 Status Registers
The status registers in the DS3112 allow the host to monitor the real-time condition of the device. Most of
the status bits in the device can cause a hardware interrupt to occur. Also, most of the status bits within
the device are latched to ensure that the host can detect changes in state and the true status of the device.
There are three types of status bits in the DS3112. The first type is called an event status bit and is
derived from a momentary condition or state that occurs within the device. The event status bits are
always cleared when read and can generate an interrupt when they are asserted. An example of an event
status bit is the one-second timer boundary occurrence (OST).
The second type of status bit is called an alarm status bit, which is derived from conditions that can occur
for longer than an instance. The alarm status bits will be cleared when read unless the alarm is still
present. The alarm status bits generate interrupts on a change in state in the alarm (i.e., when it is asserted
or deasserted). An example of an alarm status bit is the loss of frame (LOF).
The third type of status bit is called a real-time status bit. The real-time status bit remains active as long
as the condition exists and will generate an interrupt as long as the condition exists. An example of a real-
time status bit is the loss of transmit clock (LOTC).
Figure 4-1. Event Status Bit
Internal Signal
Status Bit
Interrupt
Read
Figure 4-2. Alarm Status Bit
Internal Signal
Status Bit
Interrupt
Read
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