- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄16261 > DS3112DK (Maxim Integrated Products)KIT DEMO FOR DS3112 PDF資料下載
參數(shù)資料
| 型號： | DS3112DK |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 67/133頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT DEMO FOR DS3112 |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 1 |
| 主要目的： | 接口，交叉點開關(guān)/多路復(fù)用器 |
| 已用 IC / 零件： | DS3112 |
| 已供物品： | 板，CD |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁當前第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁
DS3112
39 of 133
Figure 4-3. Real-Time Status Bit
Internal Signal
Status Bit
Interrupt
Read
4.3.2 MSR
The Master Status Register (MSR) is a special status register that can be used to help the host quickly
locate changes in device status. There is a status bit in the MSR for each of the major blocks within the
DS3112. When an alarm or event occurs in one of these blocks, the device can be configured to set a bit
in the MSR. Status bits in the MSR can also cause a hardware interrupt to occur. In either polled or
interrupt driven software routines, the host can first read the MSR to locate which status registers need to
be serviced.
Register Name:
MSR
Register Description:
Master Status Register
Register Address:
08h
Bit #
7
6
5
4
3
2
1
0
Name
—
T2E2SR2
T2E2SR1
FEAC
HDLC
BERT
COVF
OST
Default
—
Bit #
15
14
13
12
11
10
9
8
Name
—
G.747
T3E3MS
LORC
LOTC
T3E3SR
T1LB
Default
—
Note: Bits that are underlined are read-only; all other bits are read-write.
Bit 0: One-Second Timer Boundary Occurrence (OST). This latched read-only event-status bit will be set to a
one on each one-second boundary as timed by the DS3112. The device chooses an arbitrary one-second boundary
that is timed from the HRCLK signal. This bit will be cleared when read and will not be set again until another
one-second boundary has occurred. The setting of this status bit can cause a hardware interrupt to occur if the OST
bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be allowed to clear when this
bit is read.
Bit 1: Counter Overflow Event (COVF). This latched read-only event-status bit will be set to a one if any of the
error counters saturates (the error counters saturate when full). This bit will be cleared when read even if one or
more of the error counters is still saturated. The setting of this status bit can cause a hardware interrupt to occur if
the COVF bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be allowed to clear
when this bit is read.
Bit 2: Change in BERT Status (BERT). This read-only real-time status bit will be set to a one if there is a major
change of status in the BERT receiver and the associated interrupt enable bit is set in the BERTCO register. A
major change of status is defined as either a change in the receive synchronization (i.e., the BERT has gone into or
out of receive synchronization), a bit error has been detected, or an overflow has occurred in either the Bit Counter
or the Error Counter. The host must read the status bits of the BERT in the BERT Status Register (BERTEC0) to
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| RMM10DSEN | CONN EDGECARD 20POS .156 EYELET |
| DS2148DK | KIT DESIGN LIU DS2148 3/5V T1/E1 |
| H3CWH-6436G | IDC CABLE - HKC64H/AE64G/HPL64H |
| 78M6618-PDU-1 | EVAL KIT DS8005 |
| RMM10DSEH | CONN EDGECARD 20POS .156 EYELET |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS3112N | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3112N+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3112N+W | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3112NC1 | 制造商:Maxim Integrated Products 功能描述:T3 E3 MULTIPLEXER, 3.3V T3/E3 FRAMER AND M13/E13/G.747 MUX - Rail/Tube |
| DS3112ND1E | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。