參數(shù)資料
型號： DS3112+
廠商： Maxim Integrated Products
文件頁數(shù)： 61/133頁
文件大?。?/td> 0K
描述： IC MUX TEMPE T3/E3 256-BGA
產(chǎn)品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 40
控制器類型： 調幀器，多路復用器
接口： 并行/串行
電源電壓： 3.135 V ~ 3.465 V
電流 - 電源： 150mA
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 256-LBGA
供應商設備封裝： 256-PBGA（27x27）
包裝： 管件
產(chǎn)品目錄頁面： 1419 (CN2011-ZH PDF)
DS3112
33 of 133
4
MASTER DEVICE CONFIGURATION AND STATUS/INTERRUPT
4.1 Master Reset and ID Register Description
The master reset and ID (MRID) register can be used to globally reset the device. When the
RST bit is set
to one, all of the internal registers will be placed into their default state, which is 0000h. A reset can also
be invoked by the
RST hardware signal.
The upper byte of the MRID register is read-only and it can be read by the host to determine the chip
revision. Contact the factory for specifics on the meaning of the value read from the ID0 to ID7 bits.
Register Name:
MRID
Register Description:
Master Reset and ID Register
Register Address:
00h
Bit #
7
6
5
4
3
2
1
0
Name
—
T3E3RSY
T2E2RSY
RFIFOR
RST
Default
—
0
Bit #
15
14
13
12
11
10
9
8
Name
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
Default
X
Note: Bits that are underlined are read-only; all other bits are read-write.
Bit 0: Master Software Reset (RST). When this bit is set to a one by the host, it will force all of the internal
registers to their default state, which is 0000h and forces the T3/E3 and T1/E1 outputs to send an all ones pattern.
This bit must be set high for a minimum of 100ns. This software bit is logically ORed with the hardware signal
RST.
0 = normal operation
1 = force all internal registers to their default value of 0000h
Bit 1: Low-Speed (T1/E1) Receive FIFO Reset (RFIFOR). A zero to one transition on this bit will cause the
receive T1/E1 demux FIFOs to be reset, which will cause them to be flushed. See the DS3112 Block Diagrams in
Figure 1-1 and Figure 1-2 for details on the placement of the FIFOs within the chip. This bit must be cleared and
set again for a subsequent reset to occur.
Bit 2: T2/E2/G.747 Force Receive Framer Resynchronization (T2E2RSY). A zero to one transition on this bit
will cause all seven of the T2 receive framers or all four of the E2 receive framers or all seven of the G.747 framers
to resynchronize. This bit must be cleared and set again for a subsequent resynchronization to occur.
Bit 3: T3/E3 Force Receive Framer Resynchronization (T3E3RSY). A zero to one transition on this bit will
cause the T3 receive framer or the E3 receive framer to resynchronize. This bit must be cleared and set again for a
subsequent resynchronization to occur.
Bits 8 to 15: Chip Revision ID Bit 0 to 7 (ID0 to ID7). Read-only. Contact the factory for details on the meaning
of the ID bits.
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參數(shù)描述
DS3112+ 功能描述:網(wǎng)絡控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3112+W 功能描述:網(wǎng)絡控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3112D1 功能描述:網(wǎng)絡控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3112D1+ 功能描述:網(wǎng)絡控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3112DK 功能描述:網(wǎng)絡開發(fā)工具 DS3112 Dev Kit RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V
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