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參數(shù)資料
| 型號(hào)： | DS3112+ |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 132/133頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MUX TEMPE T3/E3 256-BGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 控制器類型： | 調(diào)幀器，多路復(fù)用器 |
| 接口： | 并行/串行 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 電流 - 電源： | 150mA |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-LBGA |
| 供應(yīng)商設(shè)備封裝： | 256-PBGA（27x27） |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁(yè)面： | 1419 (CN2011-ZH PDF) |
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DS3112
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10.2 FEAC Status Register Description
Register Name:
FSR
Register Description:
FEAC Status Register
Register Address:
92h
Bit #
7
6
5
4
3
2
1
0
Name
—
RFI
RFCD
Default
—
Bit #
15
14
13
12
11
10
9
8
Name
RFFO
RFFE
RFF5
RFF4
RFF3
RFF2
RFF1
RFF0
Default
—
Note: Bits that are underlined are read-only; all other bits are read-write.
Bit 0: Receive FEAC Codeword Detected (RFCD). This latched read-only event-status bit will be set to a one
each time the FEAC controller has detected and validated a new FEAC codeword. This bit will be cleared when
read and will not be set again until another new codeword is detected. The setting of this bit can cause a hardware
interrupt to occur if the FEAC bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will
be allowed to clear when this bit is read.
Bit 14: Receive FEAC FIFO Empty (RFFE). This read-only real time status bit will be set to a one when the
Receive FEAC FIFO is empty and hence the RFF0 to RFF5 bits contain no valid information.
Bit 1: Receive FEAC Idle (RFI). This latched read-only event status bit will be set to a one each time the FEAC
controller has detected 16 consecutive ones following a valid codeword. This bit will be cleared when read. The
setting of this bit can cause a hardware interrupt to occur if the IERFI bit in the FEAC Control Register (FCR) is
set to one and the FEAC bit in the Interrupt Mask for MSR (IMSR) is set to one.
Bits 8 to 13: Receive FEAC FIFO Data (RFF0 to RFF5). Data from the Receive FEAC FIFO can be read from
these bits. The FEAC codeword is of the form ...0xxxxxx011111111... where the rightmost bit is received first.
These six bits are the debounced and integrated middle six bits of the second byte of the FEAC codeword (i.e., the
six “x” bits). RFF0 is the LSB and is received first while RFF5 is the MSB and is received last.
Bit 15: Receive FEAC FIFO Overflow (RFFO). This latched read-only event-status bit will be set to a one when
the receive FEAC controller has attempted to write to an already full Receive FEAC FIFO and current incoming
FEAC codeword is lost. This bit will be cleared when read and will not be set again until another FIFO overflow
occurs (i.e., the Receive FEAC FIFO has been read and then fills beyond capacity).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| DS3112+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3112+W | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3112D1 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3112D1+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3112DK | 功能描述:網(wǎng)絡(luò)開發(fā)工具 DS3112 Dev Kit RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評(píng)估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V |
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