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參數(shù)資料
| 型號(hào)： | DS26522GN |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | Dual T1/E1/J1 Transceiver |
| 中文描述： | DATACOM, TIME SLOT 0/16 TRANSCEIVER, PBGA144 |
| 封裝： | CSBGA-144 |
| 文件頁(yè)數(shù)： | 9/258頁(yè) |
| 文件大?。?/td> | 1263K |
| 代理商： | DS26522GN |
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DS26522 Dual T1/E1/J1 Transceiver
9 of 258
1.
The DS26522 is a 2-channel device that can be software configured for T1, E1, or J1 operation. The DS26522 is a
MCM composed of two DS26521 die. Each channel is composed of a line interface unit (LIU), framer, HDLC
controller, and a TDM backplane interface, and is controlled by either an 8-bit parallel port or a serial peripheral
interface (SPI). Internal impedance matching is provided for both transmit and receive paths reducing external
component count. The DS26522 is a member of the TEX-series transceiver family and is software compatible with
the DS26521 single, DS26524 quad, and DS26528 octal transceivers.
DETAILED DESCRIPTION
The LIU is composed of a transmit interface, receive interface, and a jitter attenuator. The transmit interface is
responsible for generating the necessary waveshapes for driving the network and providing the correct source
impedance depending on the type of media used. T1 waveform generation includes DSX-1 line build-outs as well
as CSU line build-outs of 0dB, -7.5dB, -15dB, and -22.5dB. E1 waveform generation includes G.703 waveshapes
for both 75
Ω
coax and 120
Ω
twisted cables. The receive interface provides network termination and recovers clock
and data from the network. The receive sensitivity adjusts automatically to the incoming signal level and can be
programmed for 0dB to -43dB or 0dB to -12dB for E1 applications and 0dB to -15dB or 0dB to -36dB for T1
applications. The jitter attenuator removes phase jitter from the transmitted or received signal. The crystal-less jitter
attenuator requires only a T1 or E1 clock rate, or multiple thereof, for both E1 and T1 applications, and can be
placed in either transmit or receive data paths.
On the transmit side, clock, data, and frame-sync signals are provided to the framer by the backplane interface
section. The framer inserts the appropriate synchronization framing patterns, alarm information, calculates and
inserts the CRC codes, and provides the B8ZS/HDB3 (zero code suppression) and AMI line coding. The receive-
side framer decodes AMI, B8ZS, and HDB3 line coding, synchronizes to the data stream, reports alarm
information, counts framing/coding/CRC errors, and provides clock, data, and frame-sync signals to the backplane
interface section.
Both transmit and receive paths have access to an HDLC controller. The HDLC controller transmits and receives
data via the framer block. The HDLC controller can be assigned to any time slot, a portion of a time slot, or to FDL
(T1) or Sa bits (E1). Each controller has 64-byte FIFOs, reducing the amount of processor overhead required to
manage the flow of data.
The backplane interface provides a versatile method of sending and receiving data from the host system. Elastic
stores provide a method for interfacing to a system backplane, converting from a T1/E1 network to a 2.048MHz,
4.096MHz, 8.192MHz, 16.384MHz, or N x 64kHz system backplane. The elastic stores also manage slip conditions
(asynchronous interface). The interleave bus option (IBO) is provided to allow up to eight transceivers to share a
high-speed backplane. The DS26522 also contains an internal clock adapter useful for the creation of a
synchronous, high-frequency backplane timing source.
The parallel port provides access for configuration and status of all the DS26522’s features. Diagnostic capabilities
include loopbacks, PRBS pattern generation/detection, and 16-bit loop-up and loop-down code generation and
detection.
1.1
Major Operating Modes
The DS26522 has two major modes of operation: T1 mode and E1 mode. The mode of operation for the LIU is
configured in the LIU Transmit Receive Control register (
LTRCR
). The mode of operation for the framer is
configured in the Transmit Master Mode register (
TMMR
) and Receive Master Mode register (
RMMR
). J1 operation
is a special case of T1 operating mode.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS26522GN+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 2-Port E1/T1/J1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS26524 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Quad T1/E1/J1 Transceiver |
| DS26524_07 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Quad T1/E1/J1 Transceiver |
| DS26524DK | 功能描述:網(wǎng)絡(luò)開發(fā)工具 DS26524 Dev Kit RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評(píng)估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V |
| DS26524G | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4-Port E1/T1/J1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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