參數(shù)資料
型號(hào)： DS26522GN
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 數(shù)字傳輸電路
英文描述： Dual T1/E1/J1 Transceiver
中文描述： DATACOM, TIME SLOT 0/16 TRANSCEIVER, PBGA144
封裝： CSBGA-144
文件頁(yè)數(shù)： 23/258頁(yè)
文件大小： 1263K
代理商： DS26522GN
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)當(dāng)前第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)第221頁(yè)第222頁(yè)第223頁(yè)第224頁(yè)第225頁(yè)第226頁(yè)第227頁(yè)第228頁(yè)第229頁(yè)第230頁(yè)第231頁(yè)第232頁(yè)第233頁(yè)第234頁(yè)第235頁(yè)第236頁(yè)第237頁(yè)第238頁(yè)第239頁(yè)第240頁(yè)第241頁(yè)第242頁(yè)第243頁(yè)第244頁(yè)第245頁(yè)第246頁(yè)第247頁(yè)第248頁(yè)第249頁(yè)第250頁(yè)第251頁(yè)第252頁(yè)第253頁(yè)第254頁(yè)第255頁(yè)第256頁(yè)第257頁(yè)第258頁(yè)
DS26522 Dual T1/E1/J1 Transceiver
23 of 258
NAME
PIN
TYPE
FUNCTION
D[2]/
SPI_SCLK
M2
I
Data [2]/SPI Serial Interface Clock
D[2]:
Bit 2 of the 8-bit data bus used to input data during register writes, and data
outputs during register reads. Not driven when both
CSB1
and
CSB2
= 1.
SPI_SCLK:
SPI serial clock input when SPI_SEL = 1.
D[1]/
SPI_MOSI
L3
I
Data [1]/SPI Serial Interface Data Master-Out/Slave-In
D[1]:
Bit 1 of the 8-bit data bus used to input data during register writes, and data
outputs during register reads. Not driven when both
CSB1
and
CSB2
= 1.
SPI_MOSI:
SPI serial data input (master-out/slave-in) when SPI_SEL = 1.
D[0]/
SPI_MISO
M3
I
Data [0]/SPI Serial Interface Data Master-In/Slave-Out
D[0]:
Bit 0 of the 8-bit data bus used to input data during register writes, and data
outputs during register reads. Not driven when both
CSB1
and
CSB2
= 1.
SPI_MISO:
SPI serial data output (master-in/slave-out) when SPI_SEL = 1.
CSB1
L4
CSB2
M4
I
Chip-Select Bar.
This active-low signal is used to qualify register read/write
accesses. The
RDB/DSB
and
WRB
signals are qualified with
CSB1
and
CSB2
.
CSB1
and
CSB2
must not be active at the same time. If
CSB1
is active, channel
one is accessed for reading or writing. If
CSB2
is active, channel two is accessed.
RDB
/
DSB
H3
I
Read-Data Bar/Data-Strobe Bar.
This active-low signal along with
CSB
qualifies
read access to one of the DS26522 registers. The DS26522 drives the data bus
with the contents of the addressed register while
RDB
is low and
CSB1
or
CSB2
is
low.
Write-Read Bar/Read-Write Bar.
This active-low signal along with
CSBn
qualifies
write access to one of the DS26522 registers. Data at D[7:0] is written into the
addressed register at the rising edge of
WRB
while
CSB1
or
CSB2
is low.
WRB
/
RWB
J3
I
SPI_SEL
D7
I
SPI Serial Bus Mode Select
SPI:
0 = Parallel Bus Mode, 1 = SPI Serial Bus Mode
Interrupt Bar.
This active-low, open-drain output is asserted when an unmasked
interrupt event is detected.
INTB
will be deasserted when all interrupts have been
acknowledged and serviced. Extensive mask bits are provided at the global level,
framer, LIU, and BERT level.
Bus Type Select.
Set high to select Motorola bus timing, low to select Intel bus
timing. This pin controls the function of the
RDB/DSB
and
WRB
pins.
SYSTEM INTERFACE
Master Clock.
This is an independent free-running clock whose input can be a
multiple of 2.048MHz ±50ppm or 1.544MHz ±50ppm. The clock selection is
available by bits MPS0 and MPS1 and FREQSEL. Multiple of 2.048MHz can be
internally adapted to 1.544MHz. Multiple of 1.544MHz can be adapted to
2.048MHz. Note that TCLK must be 2.048MHz for E1 and 1.544MHz for T1/J1
operation. See
Table 9-12
.
Reset Bar.
Active-low reset. This input forces the complete DS26522 reset. This
includes reset of the registers, framers, and LIUs.
Reference Clock Input/Output
Input:
A 2.048MHz or 1.544MHz clock input. This clock can be used to generate
the backplane clock. This allows for the users to synchronize the system
backplane with the reference clock. The other options for the backplane clock
reference are LIU-received clocks or MCLK.
Output:
This signal can also be used to output a 1.544MHz or 2.048MHz reference
clock. This allows for multiple DS26522s to share the same reference for
generation of the backplane clock. Hence, in a system consisting of multiple
DS26522s, one can be a master and others a slave using the same reference
clock.
INTB
K4
U
BTS
E5
I
MCLK
M9
I
RESETB
K3
I
REFCLKIO1
K8
REFCLKIO2
L10
I/O
相關(guān)PDF資料
PDF描述
DS26524 Quad T1/E1/J1 Transceiver
DS2714 Quad Loose Cell NiMH Charger
DS276 Low Power Transceiver Chip(低功率的RS232收發(fā)器芯片)
DS2782 Stand-Alone Fuel Gauge IC
DS3234 Extremely Accurate SPI Bus RTC with Integrated Crystal and SRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS26522GN+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 2-Port E1/T1/J1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS26524 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Quad T1/E1/J1 Transceiver
DS26524_07 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Quad T1/E1/J1 Transceiver
DS26524DK 功能描述:網(wǎng)絡(luò)開發(fā)工具 DS26524 Dev Kit RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評(píng)估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V
DS26524G 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4-Port E1/T1/J1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*