參數(shù)資料
型號(hào): DS2152
英文描述: Enhanced T1 Single-Chip Transceiver
中文描述: 增強(qiáng)型T1單芯片收發(fā)器
文件頁(yè)數(shù): 57/94頁(yè)
文件大?。?/td> 1003K
代理商: DS2152
DS2152
57 of 93
4.
repeat step 3
5.
wait for interrupt, skip to step 3
6.
disable THALF or TNF interrupt and enable TMEND interrupt
7.
wait for an interrupt, then read TUDR status bit to make sure packet was transmitted correctly.
Transmit a BOC
1.
write 6-bit code into TBOC
2.
set SBOC bit in TBOC=1
11.1.4 HDLC/BOC Register Description
FDLC: FDL CONTROL REGISTER
(Address=00 Hex)
(MSB) (LSB)
RBR
RHR
TFS
THR
TABT
TEOM
TZSD
TCRCF
SYMBOL
POSITION
NAME AND DESCRIPTION
RBR
FDLC.7
Receive BOC Reset.
A 0 to 1 transition will reset the BOC
circuitry. Must be cleared and set again for a subsequent reset.
RHR
FDLC.6
Receive HDLC Reset.
A 0 to 1 transition will reset the HDLC
controller. Must be cleared and set again for a subsequent reset.
TFS
FDLC.5
Transmit Flag/Idle Select.
0 = 7Eh
1 = FFh
THR
FDLC.4
Transmit HDLC Reset.
A 0 to 1 transition will reset both the
HDLC controller and the transmit BOC circuitry. Must be
cleared and set again for a subsequent reset.
TABT
FDLC.3
Transmit Abort.
A 0 to 1 transition will cause the FIFO
contents to be dumped and one FEh abort to be sent followed by
7Eh or FFh flags/idle until a new packet is initiated by writing
new data into the FIFO. Must be cleared and set again for a
subsequent abort to be sent.
TEOM
FDLC.2
Transmit End of Message.
Should be set to a 1 just before the
last data byte of a HDLC packet is written into the transmit
FIFO at TFFR. This bit will be cleared by the HDLC controller
when the last byte has been transmitted.
TZSD
FDLC.1
Transmit 0 Stuffer Defeat.
Overrides internal enable.
0 = enable the 0 stuffer (normal operation)
1 = disable the 0 stuffer
TCRCD
FDLC.0
Transmit CRC Defeat.
0 = enable CRC generation (normal operation)
1 = disable CRC generation
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