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參數(shù)資料
| 型號： | DS2152 |
| 英文描述： | Enhanced T1 Single-Chip Transceiver |
| 中文描述： | 增強型T1單芯片收發(fā)器 |
| 文件頁數(shù)： | 72/94頁 |
| 文件大?。?/td> | 1003K |
| 代理商： | DS2152 |
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DS2152
72 of 93
TRANSFORMER SPECIFICATIONS
Table 14-3
SPECIFICATION
Turns Ratio
Primary Inductance
Leakage Inductance
Intertwining Capacitance
DC Resistance
RECOMMENDED VALUE
1:1 (receive) and 1:1.15 or 1:1.36 (transmit)
±
5%
600 uH minimum
1.0 uH maximum
40 pF maximum
1.2 ohms maximum
14.3 JITTER ATTENUATOR
The DS2152 contains an onboard jitter attenuator that can be set to a depth of either 32 or 128 bits via the
JABDS bit in the Line Interface Control Register (LICR). The 128-bit mode is used in applications
where large excursions of wander are expected. The 32-bit mode is used in delay sensitive applications.
The characteristics of the attenuation are shown in Figure 14-4. The jitter attenuator can be placed in
either the receive path or the transmit path by appropriately setting or clearing the JAS bit in the LICR.
Also, the jitter attenuator can be disabled (in effect, removed) by setting the DJA bit in the LICR. In order
for the jitter attenuator to operate properly, a 1.544 MHz clock (
±
50 ppm) must be applied at the MCLK
pin or a crystal with similar characteristics must be applied across the MCLK and XTALD pins. If a
crystal is applied across the MCLK and XTALD pins, then capacitors should be placed from each leg of
the crystal to the local ground plane as shown in Figure 14-1. Onboard circuitry adjusts either the
recovered clock from the clock/data recovery block or the clock applied at the TCLKI pin to create a
smooth jitter free clock which is used to clock data out of the jitter attenuator FIFO. It is acceptable to
provide a gapped/bursty clock at the TCLKI pin if the jitter attenuator is placed on the transmit side. If the
incoming jitter exceeds either 120 UIpp (buffer depth is 128 bits) or 28 UIpp (buffer depth is 32 bits),
then the DS2152 will divide the internal nominal 24.704 MHz clock by either 15 or 17 instead of the
normal 16 to keep the buffer from overflowing. When the device divides by either 15 or 17, it also sets
the Jitter Attenuator Limit Trip (JALT) bit in the Receive Information Register (RIR3.5).
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DS2152DK | 功能描述:KIT DESIGN DS2152 RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 過時/停產(chǎn)零件編號 系列:- 標準包裝:1 系列:- 傳感器類型:CMOS 成像，彩色（RGB） 傳感范圍:WVGA 接口:I²C 靈敏度:60 fps 電源電壓:5.7 V ~ 6.3 V 嵌入式:否 已供物品:成像器板 已用 IC / 零件:KAC-00401 相關產(chǎn)品:4H2099-ND - SENSOR IMAGE WVGA COLOR 48-PQFP4H2094-ND - SENSOR IMAGE WVGA MONO 48-PQFP |
| DS2152L | 功能描述:網(wǎng)絡控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2152L+ | 功能描述:網(wǎng)絡控制器與處理器 IC Enhanced T1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2152L-ES | 制造商:DALL 功能描述: |
| DS2152LN | 功能描述:網(wǎng)絡控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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