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參數資料
| 型號： | DS21352LN |
| 英文描述： | 3.3V DS21352 and 5V DS21552 T1 Single-Chip Transceivers |
| 中文描述： | 3.3 DS21352及5V DS21552 T1單芯片收發(fā)器 |
| 文件頁數： | 63/137頁 |
| 文件大?。?/td> | 1094K |
| 代理商： | DS21352LN |
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DS21352/DS21552
63 of 137
RCC1/RCC2/RCC3: RECEIVE CHANNEL CONTROL REGISTER
(ADDRESS=1B TO 1D Hex)
(MSB)
CH8
CH16
CH24
(LSB)
CH1
CH9
CH17
CH7
CH15
CH23
CH6
CH14
CH22
CH5
CH13
CH21
CH4
CH12
CH20
CH3
CH11
CH19
CH2
CH10
CH18
RCC1 (1B)
RCC2 (1C)
RCC3 (1D)
SYMBOL
CH24
POSITION
RCC3.7
NAME AND DESCRIPTION
Receive Channel 24 Code Insertion Control Bit
0 = do not insert data from the RC24 register into the receive data stream
1 = insert data from the RC24 register into the receive data stream
Receive Channel 1 Code Insertion Control Bit
0 = do not insert data from the RC1 register into the receive data stream
1 = insert data from the RC1 register into the receive data stream
CH1
RCC1.0
12. PER–CHANNEL LOOPBACK
The Transmit Idle Registers (TIRs) have an alternate function that allows them to define a Per–Channel
LoopBack (PCLB). If the TIRFS control bit (CCR4.0) is set to one, then the TIRs will determine which
channels (if any) from the backplane should be replaced with the data from the receive side or in other
words, off of the T1 line. If this mode is enabled, then transmit and receive clocks and frame syncs must
be synchronized. One method to accomplish this would be to tie RCLK to TCLK and RFSYNC to
TSYNC.
13. CLOCK BLOCKING REGISTERS
The Receive Channel Blocking Registers (RCBR1/RCBR2/RCBR3) and the Transmit Channel Blocking Registers
(TCBR1/TCBR2/TCBR3) control the RCHBLK and TCHBLK pins respectively. The RCHBLK and TCHCLK pins are user
programmable outputs that can be forced either high or low during individual channels. These outputs can be used to block
clocks to a UART or LAPD controller in Fractional T1 or ISDN–PRI applications. When the appropriate bits are set to a one,
the RCHBLK and TCHCLK pins will be held high during the entire corresponding channel time. See the timing in Section 21
for an example.
RCBR1/RCBR2/RCBR3: RECEIVE CHANNEL BLOCKING REGISTERS
(Address=6C to 6E Hex)
(MSB)
CH8
CH16
CH24
(LSB)
CH1
CH9
CH17
CH7
CH15
CH23
CH6
CH14
CH22
CH5
CH13
CH21
CH4
CH12
CH20
CH3
CH11
CH19
CH2
CH10
CH18
RCBR1 (6C)
RCBR2 (6D)
RCBR3 (6E)
SYMBOLS
CH1-24
POSITIONS
RCBR1.0-3.7
NAME AND DESCRIPTION
Receive Channel Blocking Control Bits.
0 = force the RCHBLK pin to remain low during this channel time
1 = force the RCHBLK pin high during this channel time
TCBR1/TCBR2/TCBR3: TRANSMIT CHANNEL BLOCKING REGISTERS
(Address=32 to 34 Hex)
(MSB)
CH8
CH16
CH24
(LSB)
CH1
CH9
CH17
CH7
CH15
CH23
CH6
CH14
CH22
CH5
CH13
CH21
CH4
CH12
CH20
CH3
CH11
CH19
CH2
CH10
CH18
TCBR1 (32)
TCBR2 (33)
TCBR3 (34)
SYMBOLS
CH1-24
POSITIONS
TCBR1.0-3.7
NAME AND DESCRIPTION
Transmit Channel Blocking Control Bits.
相關PDF資料 |
PDF描述 |
|---|---|
| DS21552L | 3.3V DS21352 and 5V DS21552 T1 Single-Chip Transceivers |
| DS21552LN | 3.3V DS21352 and 5V DS21552 T1 Single-Chip Transceivers |
| DS21354 | MTTF is frequently used interchangeably with MTBF |
| DS21354L | 3.3V/5V E1 Single-Chip Transceivers |
| DS21354LN | 3.3V/5V E1 Single-Chip Transceivers |
相關代理商/技術參數 |
參數描述 |
|---|---|
| DS21352LN+ | 功能描述:網絡控制器與處理器 IC T1 Single Chip Transceivers RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數量: 數據速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21354 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:3.3V/5V E1 Single-Chip Transceivers |
| DS21354DK | 功能描述:網絡開發(fā)工具 DS21354 Dev Kit RoHS:否 制造商:Rabbit Semiconductor 產品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評估:RCM6600W 數據速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V |
| DS21354G | 功能描述:網絡控制器與處理器 IC RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數量: 數據速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21354GN | 功能描述:網絡控制器與處理器 IC RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數量: 數據速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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