參數(shù)資料
型號: DS21352LN
英文描述: 3.3V DS21352 and 5V DS21552 T1 Single-Chip Transceivers
中文描述: 3.3 DS21352及5V DS21552 T1單芯片收發(fā)器
文件頁數(shù): 56/137頁
文件大小: 1094K
代理商: DS21352LN
DS21352/DS21552
56 of 137
B5
RDS0M.3
Receive DS0 Channel Bit 5.
B6
RDS0M.2
Receive DS0 Channel Bit 6.
B7
RDS0M.1
Receive DS0 Channel Bit 7.
B8
RDS0M.0
Receive DS0 Channel Bit 8.
LSB of the DS0 channel (last bit to be received).
10. SIGNALING OPERATION
Processor based (i.e., software based) signaling access and hardware based access are available.
Processor based access and hardware based access can be used simultaneously if necessary. The
processor based signaling is covered in Section 10-1 and the hardware based signaling is covered in
Section 10-2.
10.1 PROCESSOR BASED SIGNALING
The robbed–bit signaling bits embedded in the T1 stream can be extracted from the receive stream and
inserted into the transmit stream by each framer. There is a set of 12 registers for the receive side (RS1 to
RS12) and 12 registers on the transmit side (TS1 to TS12). The signaling registers are detailed below.
The CCR1.5 bit is used to control the robbed signaling bits as they appear at RSER. If CCR1.5 is set to
zero, then the robbed signaling bits will appear at the RSER pin in their proper position as they are
received. If CCR1.5 is set to a one, then the robbed signaling bit positions will be forced to a one at
RSER. If hardware based signaling is being used, then CCR1.5 must be set to zero.
相關PDF資料
PDF描述
DS21552L 3.3V DS21352 and 5V DS21552 T1 Single-Chip Transceivers
DS21552LN 3.3V DS21352 and 5V DS21552 T1 Single-Chip Transceivers
DS21354 MTTF is frequently used interchangeably with MTBF
DS21354L 3.3V/5V E1 Single-Chip Transceivers
DS21354LN 3.3V/5V E1 Single-Chip Transceivers
相關代理商/技術參數(shù)
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