參數(shù)資料
型號： DS21352LN
英文描述： 3.3V DS21352 and 5V DS21552 T1 Single-Chip Transceivers
中文描述： 3.3 DS21352及5V DS21552 T1單芯片收發(fā)器
文件頁數(shù)： 35/137頁
文件大?。?/td> 1094K
代理商： DS21352LN
DS21352/DS21552
35 of 137
CCR1: COMMON CONTROL REGISTER 1 (Address=37 Hex)
(MSB)
TESE
(LSB)
FLB
ODF
RSAO
TSCLKM
RSCLKM
RESE
PLB
SYMBOL
POSITION
NAME AND DESCRIPTION
TESE
CCR1.7
Transmit Elastic Store Enable.
0 = elastic store is bypassed
1 = elastic store is enabled
Output Data Format.
0 = bipolar data at TPOSO and TNEGO
1 = NRZ data at TPOSO; TNEGO = 0
Receive Signaling All One’s.
This bit should not be enabled if hardware signaling is
being utilized. See Section 10 for more details.
0 = allow robbed signaling bits to appear at RSER
1 = force all robbed signaling bits at RSER to one
TSYSCLK Mode Select.
0 = if TSYSCLK is 1.544 MHz
1 = if TSYSCLK is 2.048 MHz or IBO enabled (see section 20 for details on IBO
function)
RSYSCLK Mode Select.
0 = if RSYSCLK is 1.544 MHz
1 = if RSYSCLK is 2.048 MHz or IBO enabled (see section 20 for details on IBO
function)
Receive Elastic Store Enable.
0 = elastic store is bypassed
1 = elastic store is enabled
Payload Loopback.
0 = loopback disabled
1 = loopback enabled
Framer Loopback.
0 = loopback disabled
1 = loopback enabled
ODF
CCR1.6
RSAO
CCR1.5
TSCLKM
CCR1.4
RSCLKM
CCR1.3
RESE
CCR1.2
PLB
CCR1.1
FLB
CCR1.0
6.3 PAYLOAD LOOPBACK
Payload Loopback When CCR1.1 is set to a one, the DS21352/552 will be forced into Payload LoopBack
(PLB). Normally, this loopback is only enabled when ESF framing is being performed but can be enabled
also in D4 framing applications. In a PLB situation, the DS21352/552 will loop the 192 bits of pay-load
data (with BPVs corrected) from the receive section back to the transmit section. The FPS framing pat-
tern, CRC6 calculation, and the FDL bits are not looped back, they are reinserted by the DS21352/552.
When PLB is enabled, the following will occur:
1. data will be transmitted from the TPOSO and TNEGO pins synchronous with RCLK instead of TCLK
2. all of the receive side signals will continue to operate normally
3. the TCHCLK and TCHBLK signals are forced low
4. data at the TSER, TDATA, and TSIG pins is ignored
5. the TLCLK signal will become synchronous with RCLK instead of TCLK.
6.4 FRAMER LOOPBACK
When CCR1.0 is set to a one, the DS21352/552 will enter a Framer LoopBack (FLB) mode. This
loopback is useful in testing and debugging applications. In FLB, the DS21352/552 will loop data from
the transmit side back to the receive side. When FLB is enabled, the following will occur:
1. An unframed all one’s code will be transmitted at TPOSO and TNEGO
2. Data at RPOSI and RNEGI will be ignored
相關(guān)PDF資料
PDF描述
DS21552L 3.3V DS21352 and 5V DS21552 T1 Single-Chip Transceivers
DS21552LN 3.3V DS21352 and 5V DS21552 T1 Single-Chip Transceivers
DS21354 MTTF is frequently used interchangeably with MTBF
DS21354L 3.3V/5V E1 Single-Chip Transceivers
DS21354LN 3.3V/5V E1 Single-Chip Transceivers
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS21352LN+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC T1 Single Chip Transceivers RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21354 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:3.3V/5V E1 Single-Chip Transceivers
DS21354DK 功能描述:網(wǎng)絡(luò)開發(fā)工具 DS21354 Dev Kit RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V
DS21354G 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21354GN 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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