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參數(shù)資料
| 型號(hào)： | DS1077Z-66 |
| 廠商： | DALLAS SEMICONDUCTOR |
| 元件分類： | Clock Generator |
| 英文描述： | 66.666 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| 封裝： | 0.150 INCH, SOIC-8 |
| 文件頁(yè)數(shù)： | 16/17頁(yè) |
| 文件大?。?/td> | 103K |
| 代理商： | DS1077Z-66 |
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DS1077
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Accordingly, the following bus conditions have been defined:
Bus not busy: Both data and clock lines remain HIGH.
Start data transfer: A change in the state of the data line, from HIGH to LOW, while the clock is
HIGH, defines a START condition.
Stop data transfer: A change in the state of the data line, from LOW to HIGH, while the clock line is
HIGH, defines the STOP condition.
Data valid: The state of the data line represents valid data when, after a START condition, the data line is
stable for the duration of the HIGH period of the clock signal. The data on the line must be changed
during the LOW period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a START condition and terminated with a STOP condition. The
number of data bytes transferred between START and STOP conditions is not limited, and is determined
by the master device. The information is transferred byte-wise and each receiver acknowledges with a
ninth bit.
Within the bus specifications a regular mode (100kHz clock rate) and a fast mode (400kHz clock rate) are
defined. The DS1077 works in both modes.
Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the
reception of each byte. The master device must generate an extra clock pulse which is associated with
this acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into account. When the DS1077 EEPROM is being written to,
it will not be able to perform additional responses. In this case, the slave DS1077 will send a not
acknowledge to any data transfer request made by the master. It will resume normal operation when the
EEPROM operation is complete.
A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that
has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the
master to generate the STOP condition.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS1077Z-125 | 125 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| DS1077Z-100 | 100 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| DS1100U-175/T&R | SILICON DELAY LINE, TRUE OUTPUT, PDSO8 |
| DS1100U-40/T&R | SILICON DELAY LINE, TRUE OUTPUT, PDSO8 |
| DS1100U-45/T&R | SILICON DELAY LINE, TRUE OUTPUT, PDSO8 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS1077Z-66+ | 功能描述:可編程振蕩器 EconOscillator/Dvdr 66MHz 118mil 2-Wire RoHS:否 制造商:IDT 封裝 / 箱體:5 mm x 7 mm x 1.5 mm 頻率:15.476 MHz to 866.67, 975 MHz to 1300 MHz 頻率穩(wěn)定性:+/- 50 PPM 電源電壓:3.63 V 負(fù)載電容:10 pF 端接類型:SMD/SMT 輸出格式:LVPECL 最小工作溫度:- 40 C 最大工作溫度:+ 85 C 尺寸:7 mm W x 5 mm L x 1.5 mm H 封裝: |
| DS10-80B | 制造商:TRANSMISSION DEVELOPMENTS 功能描述:MOULDED SPUR GEAR 1.0, 80 |
| DS1080CL | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Spread-Spectrum Crystal Multiplier |
| DS1080CLU+ | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Spread-Spectrum Crystal Multiplier RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| DS1080CLU+T | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Spread-Spectrum Crystal Multiplier RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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