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參數(shù)資料
| 型號： | DS1077Z-66 |
| 廠商： | DALLAS SEMICONDUCTOR |
| 元件分類： | Clock Generator |
| 英文描述： | 66.666 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| 封裝： | 0.150 INCH, SOIC-8 |
| 文件頁數(shù)： | 14/17頁 |
| 文件大?。?/td> | 103K |
| 代理商： | DS1077Z-66 |
DS1077
6 of 17
EN0 (bit)
(Default EN0=1)
If EN0=1 and PDN0= 0 the CTRL0 pin functions as an Output Enable for OUT0, the frequency of the
output being determined by the SEL0 bit.
If PDN0=1, the EN0 bit is ignored, CTRL0 will function as a power down, output OUT0 will always be
enabled on power up, its frequency being determined by the SEL0 bit.
If EN0= 0 the function of CTRL0 is determined by the SEL0 and PDN0 bits
(Refer to Table 1)
SEL0
(Default SEL0=1)
If SEL0=1 and EN0=PDN0=0 the CTRL0 pin determines the state of the MUX, (i.e., the output frequency
of OUT0)
If CTRL0=0 the output will be the Master clock frequency
If CTRL0=1 the output will be the output frequency of the M prescaler
If either EN0 or PDN0 = 1 then SEL0 determines the frequency of OUT0 when it is enabled.
If SEL0=0 the output will be the Master clock frequency
If SEL0=1 the output will be the output frequency of the M prescaler
(Refer to Table 1)
PDN0
(Default PDN=0)
This bit (if set to 1) causes CTRL0 to perform a power down function, regardless of the setting of the
other bits
If PDN0=0 the function of CTRL0 is determined by the values of EN0 and SEL0
Note: When EN0=SEL0=PDN0=0, CTRL0 also functions as a power down. This is a special case
where all the OUT0 circuitry is disabled even when the device is powered up for power to
saving when OUT0 is not used. (Refer Table 1)
PDN1
(Default PDN1=0)
If PDN1=1, CTRL1 will function as a power down
If PDN=0, CTRL1 functions as an output enable for OUT1 only
(Refer to Table 2)
Note on Output Enable and Power Down:
1. Both enables are “smart” and wait for the output to be low before going to Hi-Z
2. Power down sequence first disables both outputs before powering down the device
3. On power up the outputs are disabled until the clock has stabilized ( ~8000 cycles)
4. In power down mode the device can not be programmed
5. A power down command must persist for at least 2 cycles of the lowest output frequency plus 10
microseconds.
DIV WORD
msb
lsb
msb
lsb
n9
n8
n7
n6
n5
n4
n3
n2
n1
n0
XXXXXX
first data byte
second data byte
N
These ten bits determine the value of the programmable divider (N). The range of divisor values is from 2
to 1025, and is equal to the programmed value of N plus 2.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DS1077Z-66+ | 功能描述:可編程振蕩器 EconOscillator/Dvdr 66MHz 118mil 2-Wire RoHS:否 制造商:IDT 封裝 / 箱體:5 mm x 7 mm x 1.5 mm 頻率:15.476 MHz to 866.67, 975 MHz to 1300 MHz 頻率穩(wěn)定性:+/- 50 PPM 電源電壓:3.63 V 負載電容:10 pF 端接類型:SMD/SMT 輸出格式:LVPECL 最小工作溫度:- 40 C 最大工作溫度:+ 85 C 尺寸:7 mm W x 5 mm L x 1.5 mm H 封裝: |
| DS10-80B | 制造商:TRANSMISSION DEVELOPMENTS 功能描述:MOULDED SPUR GEAR 1.0, 80 |
| DS1080CL | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Spread-Spectrum Crystal Multiplier |
| DS1080CLU+ | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Spread-Spectrum Crystal Multiplier RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| DS1080CLU+T | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Spread-Spectrum Crystal Multiplier RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
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